device.h

vt6528芯片交换机API函数和文档运行程序

#define ASIC_STADATA        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa018))
#define ASIC_STACON         (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa01c))
#define ASIC_CAMEN          (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa028))
#define ASIC_EMISSCNT       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa03c))
#define ASIC_EPZCNT         (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa040))
#define ASIC_ERMPZCNT       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa044))
#define ASIC_ETXSTAT        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9040))
#define ASIC_MACRXDESTR     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa064))
#define ASIC_MACRXSTATEM    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa090))
#define ASIC_MACRXFIFO      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa200))




//
// Bits in the ASIC_SYS_SYSCFG register
//
#define SYSCFG_CE               0x00000002


//
// Bits in the ASIC_INT_MODE register
//
#define MODE_ALLFIQ             0x001FFFFF


//
// Bits in the ASIC_INT_PEND register
//
#define PEND_CLSALL             0x001FFFFF


//
// Interrupt vector for each device
//
#define VEC_EXT0_INT            0
#define VEC_EXT1_INT            1
#define VEC_EXT2_INT            2
#define VEC_EXT3_INT            3
#define VEC_UART0_TX_INT        4
#define VEC_UART0_RX_ERR_INT    5
#define VEC_UART1_TX_INT        6
#define VEC_UART1_RX_ERR_INT    7
#define VEC_GDMA0_INT           8
#define VEC_GDMA1_INT           9
#define VEC_TIMER0_INT          10
#define VEC_TIMER1_INT          11
#define VEC_HDLC_A_TX_INT       12
#define VEC_HDLC_A_RX_INT       13
#define VEC_HDLC_B_TX_INT       14
#define VEC_HDLC_B_RX_INT       15
#define VEC_BDMA_TX_INT         16
#define VEC_BDMA_RX_INT         17
#define VEC_MAC_TX_INT          18
#define VEC_MAC_RX_INT          19
#define VEC_I2C_INT             20
#define VEC_GLOBAL_INT          21


//
// Bits in the ASIC_INT_MASK register
//
#define MASK_EXT0_INT           (0x00000001)
#define MASK_EXT1_INT           (0x00000001 << VEC_EXT1_INT)
#define MASK_EXT2_INT           (0x00000001 << VEC_EXT2_INT)
#define MASK_EXT3_INT           (0x00000001 << VEC_EXT3_INT)
#define MASK_UART0_TX_INT       (0x00000001 << VEC_UART0_TX_INT)
#define MASK_UART0_RX_ERR_INT   (0x00000001 << VEC_UART0_RX_ERR_INT)
#define MASK_UART1_TX_INT       (0x00000001 << VEC_UART1_TX_INT)
#define MASK_UART1_RX_ERR_INT   (0x00000001 << VEC_UART1_RX_ERR_INT)
#define MASK_GDMA0_INT          (0x00000001 << VEC_GDMA0_INT)
#define MASK_GDMA1_INT          (0x00000001 << VEC_GDMA1_INT)
#define MASK_TIMER0_INT         (0x00000001 << VEC_TIMER0_INT )
#define MASK_TIMER1_INT         (0x00000001 << VEC_TIMER1_INT )
#define MASK_HDLC_A_TX_INT      (0x00000001 << VEC_HDLC_A_TX_INT )
#define MASK_HDLC_A_RX_INT      (0x00000001 << VEC_HDLC_A_RX_INT )
#define MASK_HDLC_B_TX_INT      (0x00000001 << VEC_HDLC_B_TX_INT )
#define MASK_HDLC_B_RX_INT      (0x00000001 << VEC_HDLC_B_RX_INT )
#define MASK_BDMA_TX_INT        (0x00000001 << VEC_BDMA_TX_INT )
#define MASK_BDMA_RX_INT        (0x00000001 << VEC_BDMA_RX_INT )
#define MASK_MAC_TX_INT         (0x00000001 << VEC_MAC_TX_INT )
#define MASK_MAC_RX_INT         (0x00000001 << VEC_MAC_RX_INT )
#define MASK_I2C_INT            (0x00000001 << VEC_I2C_INT )
#define MASK_GLOBAL_INT         (0x00000001 << VEC_GLOBAL_INT)
#define MASK_ALL                0x003FFFFF


//
// Bits in the ASIC_IOP_CON register
//
#define IOPCON_IRQ0_MODE_LEVEL  0x00000000
#define IOPCON_IRQ0_MODE_RISE   0x00000001
#define IOPCON_IRQ0_MODE_FALL   0x00000002
#define IOPCON_IRQ0_MODE_BOTH   0x00000003
#define IOPCON_IRQ0_FIL_ON      0x00000004
#define IOPCON_IRQ0_ACT_HIGH    0x00000008
#define IOPCON_IRQ0_ENABLE      0x00000010
#define IOPCON_DRQ0_ACT_HIGH    0x00100000
#define IOPCON_DRQ0_FIL_ON      0x00200000
#define IOPCON_DRQ0_ENABLE      0x00400000
#define IOPCON_DRQ1_ACT_HIGH    0x00800000
#define IOPCON_DRQ1_FIL_ON      0x01000000
#define IOPCON_DRQ1_ENABLE      0x02000000
#define IOPCON_DAK0_ACT_HIGH    0x04000000
#define IOPCON_DAK0_ENABLE      0x08000000
#define IOPCON_DAK1_ACT_HIGH    0x10000000
#define IOPCON_DAK1_ENABLE      0x20000000


//
// Bits in the ASIC_IOP_DATA register
//
#define IOP_DATA_P0             0x00000001
#define IOP_DATA_P1             0x00000002
#define IOP_DATA_P2             0x00000004
#define IOP_DATA_P3             0x00000008


//
// Bits in the ASIC_GDMA_CON0 register
//
#define GDMACON0_RUN            0x00000001
#define GDMACON0_BUSY           0x00000002
#define GDMACON0_EXTDREQ        0x00000004
#define GDMACON0_DST_DEC        0x00000010
#define GDMACON0_SRC_DEC        0x00000020
#define GDMACON0_DST_FIX        0x00000040
#define GDMACON0_SRC_FIX        0x00000080
#define GDMACON0_DMA_INT_EN     0x00000100
#define GDMACON0_BLOCK          0x00000800
#define GDMACON0_TX_HALFWORD    0x00001000
#define GDMACON0_DEMAND         0x00008000


//
// Bits in the ASIC_GDMA_CON1 register
//
#define GDMACON1_RUN            0x00000001
#define GDMACON1_BUSY           0x00000002
#define GDMACON1_EXTDREQ        0x00000004
#define GDMACON1_DST_DEC        0x00000010
#define GDMACON1_SRC_DEC        0x00000020
#define GDMACON1_DST_FIX        0x00000040
#define GDMACON1_SRC_FIX        0x00000080
#define GDMACON1_DMA_INT_EN     0x00000100
#define GDMACON1_BLOCK          0x00000800
#define GDMACON1_TX_HALFWORD    0x00001000
#define GDMACON1_DEMAND         0x00008000


//
// Bits in the ASIC_UART_LCON register
//
#define LCON_DATA_BITS_5        0x00
#define LCON_DATA_BITS_6        0x01
#define LCON_DATA_BITS_7        0x02
#define LCON_DATA_BITS_8        0x03

#define LCON_STOP_BITS_1        0x00
#define LCON_STOP_BITS_2        0x04

#define LCON_PARITY_NONE        0x00
#define LCON_PARITY_ODD         0x20
#define LCON_PARITY_EVEN        0x28

#define LCON_UART_CLK_INR       0x00
#define LCON_UART_CLK_EXT       0x40


//
// Bits in the ASIC_UART_CONT register
//
#define CONT_RX_DISABLE         0x00
#define CONT_RX_INT_ENABLE      0x01
#define CONT_ERR_INT_ENABLE     0x04

#define CONT_TX_DISABLE         0x00
#define CONT_TX_INT_ENABLE      0x08

#define CONT_MODE_NORMAL        0x00
#define CONT_MODE_LOOP_BACK     0x80


//
// Bits in the ASIC_UART_STAT register
//
#define STAT_RX_READY           0x20
#define STAT_TX_EMPTY           0x40


//
// Baud rates for UART
//
#define BRD_BAUDRATE_9600       (162 << 4)
#define BRD_BAUDRATE_19200      (80 << 4)
#define BRD_BAUDRATE_38400      (40 << 4)
#define BRD_BAUDRATE_57600      (26 << 4)
#define BRD_BAUDRATE_115200     (13 << 4)
#define BRD_BAUDRATE_230400     (6 << 4)
#define BRD_BAUDRATE_460800     (2 << 4)




//--------------------------------------
// SYSTEM CLOCK (for DRAM refresh & UART)
//--------------------------------------
#define fMCLK_MHz               50000000
#define MHz                     1000000
#define fMCLK                   (fMCLK_MHz / MHz)


/*---------------------  Export Types  ------------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Classes  ----------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Functions  --------------------------*/




#endif /* __DEVICE_H__ */