device.h

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    device.h
 *
 * Purpose:
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 */


#ifndef __DEVICE_H__
#define __DEVICE_H__

#if !defined(__TTYPE_H__)
#include "ttype.h"
#endif




/*---------------------  Export Definitions  ------------------------*/

/*************************************************************************/
/* Format of the Program Status Register                                 */
/*************************************************************************/
/*                                                                       */
/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
/*                                                                       */
/* Processor Mode and Mask                                               */
/*                                                                       */
/*************************************************************************/

#define I_Bit           0x80            //IRQ disable
#define F_Bit           0x40            //FIQ disable
#define T_Bit           0x20            //Thumb state, read only
#define IFRQ_DISABLE    0xC0            //Interrupt disable mask value
#define IFRQ_ENABLE     0x00            //Interrupt enable mask value
#define IFRQ_MASK       0xC0            //Interrupt lockout mask value

#define UND_MODE        0x1B            //(UND) Undefine Mode
#define ABT_MODE        0x17            //(ABT) Abort Mode
#define SVC_MODE        0x13            //(SVC) Supervisor Mode
#define IRQ_MODE        0x12            //(IRQ) Interrupt Mode
#define FIQ_MODE        0x11            //(FIQ) Fast Interrupt Mode
#define USR_MODE        0x10            //(USR) User Mode
#define SYS_MODE        0x1F            //(SYS) System Mode
#define MODE_MASK       0x1F            //Processor Mode Mask


//--------------------------------------
// Memory area layout definition
//--------------------------------------
#define ASIC_DRAM_BASE_ADDR         0x00000000
#define ASIC_LOADER_RUN_BASE_ADDR   0x00020000
#define ASIC_VEC_TBL_BASE_ADDR      0x00F00000  // limit addr of exception vector table
#define ASIC_DRAM_SIZE              0x01000000  // size == 8MB x 2 == 16MB

#define ASIC_ROM_BASE_ADDR          0x01000000
#define ASIC_ROM_0_SIZE             0x00400000  // size == 4MB
#define ASIC_ROM_1_SIZE             0x00400000  // size == 4MB
                                                // Although if when physically ROM0 is 512KB
                                                // but we still configure it as 4MB anyway

#define ASIC_EXTIO_BASE_ADDR        0x03600000
#define ASIC_CPUIF_BASE_ADDR        ((ASIC_EXTIO_BASE_ADDR + 0x4000) | ASIC_NON_CACHE_ADDR) // base addr of CPU IF
#define ASIC_MODULE_BASE_ADDR       ((ASIC_EXTIO_BASE_ADDR + 0x8000) | ASIC_NON_CACHE_ADDR) // base addr of Module card




//--------------------------------------
// Special Register Start Address After System Reset
//--------------------------------------
#define ASIC_SOC_BASE_ADDR          0x03FF0000
#define ASIC_NON_CACHE_ADDR         0x04000000  // address offset for non-cache access


//--------------------------------------
// CACHE TAG RAM
//--------------------------------------
#define ASIC_CACHE_SET0_BASE_ADDR   0x10000000  // size == 4KB
#define ASIC_CACHE_SET1_BASE_ADDR   0x10800000  // size == 4KB
#define ASIC_CACHE_TAGRAM_BASE_ADDR 0x11000000  // size == 256 x 4-byte = 1KB
#define ASIC_CACHE_TAGRAM_SIZE      256




//--------------------------------------
// System Manager
//--------------------------------------
#define ASIC_SYS_SYSCFG     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x0000))

#define ASIC_SYS_CLKCON     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3000))
#define ASIC_SYS_EXTACON0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3008))
#define ASIC_SYS_EXTACON1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x300C))
#define ASIC_SYS_EXTDBWTH   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3010))
#define ASIC_SYS_ROMCON0    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3014))
#define ASIC_SYS_ROMCON1    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3018))
#define ASIC_SYS_ROMCON2    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x301C))
#define ASIC_SYS_ROMCON3    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3020))
#define ASIC_SYS_ROMCON4    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3024))
#define ASIC_SYS_ROMCON5    (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3028))
#define ASIC_SYS_DRAMCON0   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x302C))
#define ASIC_SYS_DRAMCON1   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3030))
#define ASIC_SYS_DRAMCON2   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3034))
#define ASIC_SYS_DRAMCON3   (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x3038))
#define ASIC_SYS_REFEXTCON  (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x303C))


//--------------------------------------
// Interrupt Controller
//--------------------------------------
#define ASIC_INT_MODE       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4000))
#define ASIC_INT_PEND       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4004))
#define ASIC_INT_MASK       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4008))
#define ASIC_INT_PRI0       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x400C))
#define ASIC_INT_PRI1       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4010))
#define ASIC_INT_PRI2       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4014))
#define ASIC_INT_PRI3       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4018))
#define ASIC_INT_PRI4       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x401C))
#define ASIC_INT_PRI5       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4020))
#define ASIC_INT_OFFSET     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x4024))


//--------------------------------------
// I/O Port Interface
//--------------------------------------
#define ASIC_IOP_MOD        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5000))
#define ASIC_IOP_CON        (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5004))
#define ASIC_IOP_DATA       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x5008))


//--------------------------------------
// Timer 0, 1
//--------------------------------------
#define ASIC_TMR_TMOD       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6000))
#define ASIC_TMR_TDATA0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6004))
#define ASIC_TMR_TDATA1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6008))
#define ASIC_TMR_TCNT0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x600C))
#define ASIC_TMR_TCNT1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x6010))


//--------------------------------------
// GDMA 0
//--------------------------------------
#define ASIC_GDMA_CON0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB000))
#define ASIC_GDMA_SRC0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB004))
#define ASIC_GDMA_DST0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB008))
#define ASIC_GDMA_CNT0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xB00C))

//--------------------------------------
// GDMA 1
//--------------------------------------
#define ASIC_GDMA_CON1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC000))
#define ASIC_GDMA_SRC1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC004))
#define ASIC_GDMA_DST1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC008))
#define ASIC_GDMA_CNT1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xC00C))


//--------------------------------------
// UART 0
//--------------------------------------
#define ASIC_UART_LCON0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD000))
#define ASIC_UART_CONT0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD004))
#define ASIC_UART_STAT0     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD008))
#define ASIC_UART_TXB0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD00C))
#define ASIC_UART_RXB0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD010))
#define ASIC_UART_BRD0      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xD014))

//--------------------------------------
// UART 1
//--------------------------------------
#define ASIC_UART_LCON1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE000))
#define ASIC_UART_CONT1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE004))
#define ASIC_UART_STAT1     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE008))
#define ASIC_UART_TXB1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE00C))
#define ASIC_UART_RXB1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE010))
#define ASIC_UART_BRD1      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xE014))


//--------------------------------------
// Ethernet BDMA Register
//--------------------------------------
#define ASIC_BDMATXCON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9000))
#define ASIC_BDMARXCON      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9004))
#define ASIC_BDMATXPTR      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9008))
#define ASIC_BDMARXPTR      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x900c))
#define ASIC_BDMARXLSZ      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9010))
#define ASIC_BDMASTAT       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9014))

// Content Address Memory
#define ASIC_CAM_BASE       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9100))
#define ASIC_CAM_Reg(x)     (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9100 + (x * 0x4)))

#define ASIC_BDMATXBUF      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9200))
#define ASIC_BDMARXBUF      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0x9800))


//--------------------------------------
// Ethernet MAC Register
//--------------------------------------
#define ASIC_MACCON         (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa000))
#define ASIC_CAMCON         (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa004))
#define ASIC_MACTXCON       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa008))
#define ASIC_MACTXSTAT      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa00c))
#define ASIC_MACRXCON       (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa010))
#define ASIC_MACRXSTAT      (*VPUINT32 (ASIC_SOC_BASE_ADDR + 0xa014))