piport.c

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    piport.c
 *
 * Purpose: Port module UI callback functions
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#include "swport.h"
#include "piportmp.h"
#include "pigencfg.h"
#include "pieeprom.h"
#include "piport.h"
#include "str.h"
#if !defined(__NVRAM_H__)
#include "nvram.h"
#endif
#include "pidef.h"
#include "pimod.h"
#include "swmsg.h"




/*---------------------  Static Definitions -------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/

/*---------------------  Export Variables  --------------------------*/

/*---------------------  Export Macros  -----------------------------*/

/*---------------------  Export Functions  --------------------------*/
void PIPORT_vSetEepDefault (SPortPageCfg* pSPageCfg_Port, BOOL bWriteDefault)
{
    SMegaPortCfg SMegaPortCfgDefault = {
        DEFAULT_PORT_ENABLE,
        DEFAULT_PORT_AUTO,
        DEFAULT_PORT_SPD_DPX,
        DEFAULT_FLOW_CONTROL
    };

    // sizeof(SPerPortCfg) = 1 Byte
    STR_pvMemset(pSPageCfg_Port->aSMegaPortCfg, *((PUINT8)(&SMegaPortCfgDefault)), SWITCH_MEGA_PORT_NUM);

    // module card does not exist in default.
    // After writing default, module detection function should be run, it would write default value of module port   
    if (bWriteDefault) {
        // Set value to nvram software cache.
        g_pu8NVRSwCache[EEP_ADDR_MOD_CARD_TYPE - NVR_ADDR_DATA_AREA_START] = MOD_CARD_NA;
        g_pu8NVRSwCache[(EEP_ADDR_MOD_CARD_TYPE+1) - NVR_ADDR_DATA_AREA_START] = MOD_CARD_NA;   
        
        STR_pvMemcpy(g_pu8NVRSwCache + (EEP_ADDR_MEGA_PORT_CFG - NVR_ADDR_DATA_AREA_START), (PUINT8)pSPageCfg_Port, EEP_SIZE_MEGA_PORT_CFG);        
    }
    else {
        NVRAM_bWriteU8(EEP_ADDR_MOD_CARD_TYPE, MOD_CARD_NA);
        NVRAM_bWriteU8(EEP_ADDR_MOD_CARD_TYPE+1, MOD_CARD_NA);

        PIEEP_vSetCfgIntoEep((PUINT8)pSPageCfg_Port, EEP_ADDR_MEGA_PORT_CFG, EEP_SIZE_MEGA_PORT_CFG);
        NVRAM_vUpdateChecksum(EEP_SIZE_DATA_AREA);    
    }
}


UINT8 PIPORT_byOp(SPortPageCfg* pSPageCfg_Port, UINT8 byOp, PUINT8 pbyRtnPortId)
{
    UINT32  dwPhyPortMask;
    UINT8    byPhyPID, byLogPortIndex, byGigaPortId;


    //check if is module trk => the configs of two modules must be the same when setting configs
    if (g_bIsModuleTrk && (byOp == PORT_OP_BUF_TO_EEP_HW)) {
        if ((pSPageCfg_Port->aSGigaPortCfg[0].f2Enable != pSPageCfg_Port->aSGigaPortCfg[1].f2Enable) ||
            (pSPageCfg_Port->aSGigaPortCfg[0].f2Auto != pSPageCfg_Port->aSGigaPortCfg[1].f2Auto) ||
            (pSPageCfg_Port->aSGigaPortCfg[0].f4SpdDpx != pSPageCfg_Port->aSGigaPortCfg[1].f4SpdDpx) ||
            (pSPageCfg_Port->aSGigaPortCfg[0].f2FC != pSPageCfg_Port->aSGigaPortCfg[1].f2FC))
                
            return PORT_OP_MOD_TRK_DIFF_PORT_CFG;
    }

    for (byLogPortIndex=0; byLogPortIndex<g_byModTrkLogIdNum; byLogPortIndex++) {
        dwPhyPortMask = PIPORTMP_dwLogIdToPhyMsk(g_abyModTrkLogIdList[byLogPortIndex]);
                        
        for (byPhyPID=0; byPhyPID<SWITCH_PORT_NUM; byPhyPID++) {
            
            if (dwPhyPortMask & 0x00000001) {
                byGigaPortId = byPhyPID - SWITCH_GIGA_PORT_ID_BASE;

                if (byOp == PORT_OP_EEP_TO_BUF) {
                    if (byPhyPID < SWITCH_MEGA_PORT_NUM) {
                        PIEEP_vGetCfgFromEep(EEP_ADDR_MEGA_PORT_CFG + byPhyPID,
                                             EEP_SIZE_MEGA_PORT_OFFSET,
                                             (PUINT8)(pSPageCfg_Port->aSMegaPortCfg + byLogPortIndex));
                    }
                    break;
                }
                // buf to eep and hw, save operation
                else { //if ((byOp == PORT_OP_BUF_TO_HW)||(byOp == PORT_OP_BUF_TO_EEP_HW))
                    if (byPhyPID < SWITCH_MEGA_PORT_NUM) {
                        // set port enable
                        SWPORT_vSetPortEn(byPhyPID, pSPageCfg_Port->aSMegaPortCfg[byLogPortIndex].f1Enable);
                        // set port abl
                        if (OP_OK != SWPORT_bySetSpdDpx(byPhyPID, pSPageCfg_Port->aSMegaPortCfg[byLogPortIndex].f1Auto,
                                                                  pSPageCfg_Port->aSMegaPortCfg[byLogPortIndex].f3SpdDpx)) {
                            *pbyRtnPortId = g_abyModTrkLogIdList[byLogPortIndex];
                            return PORT_OP_WRONG_AUTO_ABY;
                        }
                        // set port flowctrl
                        SWPORT_vSetFlowCtrlEn(byPhyPID, pSPageCfg_Port->aSMegaPortCfg[byLogPortIndex].f1FC);
                    }
                    else {  // for giga ports
                        // set port enable
                        SWPORT_vSetPortEn(byPhyPID, pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f2Enable);
                        if (pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f2Enable != FALSE) {
                            // set port abl, the value should be transferred by specified SStrTblMap
                            if (OP_OK != SWPORT_bySetSpdDpx(byPhyPID, pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f2Auto,
                                                                      pSPageCfg_Port->aSStrTblMap[byGigaPortId][2].abyListIndex[pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f4SpdDpx])) {
                                *pbyRtnPortId = g_abyModTrkLogIdList[byLogPortIndex];
                                return PORT_OP_WRONG_AUTO_ABY;
                            }
                            // set port flowctrl
                            SWPORT_vSetFlowCtrlEn(byPhyPID, pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f2FC);
                        }
                    }

                    if (byOp == PORT_OP_BUF_TO_EEP_HW) {    //Save

                        if (byPhyPID < SWITCH_MEGA_PORT_NUM) {
                            PIEEP_vSetCfgIntoEep((PUINT8)(pSPageCfg_Port->aSMegaPortCfg + byLogPortIndex),
                                                 EEP_ADDR_MEGA_PORT_CFG + byPhyPID,
                                                 EEP_SIZE_MEGA_PORT_OFFSET);
                        }
                        else {  // for giga ports
                            PIEEP_vSetCfgIntoEep((PUINT8)(pSPageCfg_Port->aSGigaPortCfg + byGigaPortId),
                                                 EEP_ADDR_GIGA_PORT_CFG + EEP_SIZE_GIGA_PORT_OFFSET * byGigaPortId,
                                                 EEP_SIZE_GIGA_PORT_OFFSET);
                        }
                    }
                }   // end if byOp
            }   // end if (dwPhyPortMask & 0x00000001)
            dwPhyPortMask >>= 1;
        } // end for byPhyPID
    } // end for byLogPortIndex

    if (byOp == PORT_OP_BUF_TO_EEP_HW) {    //Save
        NVRAM_vUpdateChecksum(EEP_SIZE_DATA_AREA);
    }
    // init string table mapping of giga port config
    else if (byOp == PORT_OP_EEP_TO_BUF) {  //Load
        for (byGigaPortId = 0; byGigaPortId < SWITCH_GIGA_PORT_NUM; byGigaPortId++)
        {
            PIEEP_vGetCfgFromEep(EEP_ADDR_GIGA_PORT_CFG + EEP_SIZE_GIGA_PORT_OFFSET * byGigaPortId,
                                 EEP_SIZE_GIGA_PORT_OFFSET,
                                 (PUINT8)(pSPageCfg_Port->aSGigaPortCfg + byGigaPortId));

            if (pSPageCfg_Port->aSGigaPortCfg[byGigaPortId].f2Enable == LISTBOX_ENDIS_NA)
            {
                pSPageCfg_Port->abyGigaPortName[byGigaPortId] = MOD_CARD_TYPE_NUM * byGigaPortId;

                for (byLogPortIndex=0; byLogPortIndex<4; byLogPortIndex++)
                {
                    pSPageCfg_Port->aSStrTblMap[byGigaPortId][byLogPortIndex].abyListIndex = g_aSStrMapSpdDup[0].abyListIndex;
                    pSPageCfg_Port->aSStrTblMap[byGigaPortId][byLogPortIndex].byListNum = 0;
                }
            }
            else
            {
                byPhyPID = PIMOD_byGetModuleType(byGigaPortId);

                pSPageCfg_Port->abyGigaPortName[byGigaPortId] = byPhyPID + MOD_CARD_TYPE_NUM * byGigaPortId;

                // enable
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][0].abyListIndex = g_aSStrMapSpdDup[0].abyListIndex;
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][0].byListNum = 2;
                // auto
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][1].abyListIndex = g_aSStrMapSpdDup[0].abyListIndex;
                if (g_aSStrMapSpdDup[byPhyPID].abyListIndex[0] == PORT_SPDPX_AUTO)
                    pSPageCfg_Port->aSStrTblMap[byGigaPortId][1].byListNum = 2;
                else
                    pSPageCfg_Port->aSStrTblMap[byGigaPortId][1].byListNum = 0;
                // spd/dup
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][2].abyListIndex = g_aSStrMapSpdDup[byPhyPID].abyListIndex;
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][2].byListNum = g_aSStrMapSpdDup[byPhyPID].byListNum;
                // flow control
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][3].abyListIndex = g_aSStrMapSpdDup[0].abyListIndex;
                pSPageCfg_Port->aSStrTblMap[byGigaPortId][3].byListNum = 2;
            }
        } // end for
    }
    
    return OP_OK;
}

void PIPORT_vGetPortStatus(SPortStatusPage *pSPage_PortStatus)
{
    UINT8   byPhyPID, byPanelPortID=0;
    SPortStatus SPortStatusNA = {LISTBOX_ENDIS_NA, LISTBOX_LINK_NA, PORT_SPDPX_NA, LISTBOX_ONOFF_NA};


    for (byPanelPortID=0; byPanelPortID<SWITCH_PORT_NUM; byPanelPortID++)
    {
        // set to default value
        STR_pvMemcpy(pSPage_PortStatus->aSPortStatus + byPanelPortID, &SPortStatusNA, sizeof(SPortStatus));

        byPhyPID = PIPORTMP_byLogIdToPhyId(byPanelPortID);

        if ((byPhyPID >= SWITCH_GIGA_PORT_ID_BASE)
            && (! PIMOD_byGetModuleType(byPhyPID - SWITCH_GIGA_PORT_ID_BASE)) )
            continue;

        // get port enable
        pSPage_PortStatus->aSPortStatus[byPanelPortID].f2Enable = SWPORT_bGetPortEn(byPhyPID);

        if (pSPage_PortStatus->aSPortStatus[byPanelPortID].f2Enable)
        {
            // get link state
            pSPage_PortStatus->aSPortStatus[byPanelPortID].f2LinkUp = SWPORT_bGetLinkSts(byPhyPID);
            if (pSPage_PortStatus->aSPortStatus[byPanelPortID].f2LinkUp)
            {
                // get spd/dpx
                pSPage_PortStatus->aSPortStatus[byPanelPortID].f4SpdDpx = SWPORT_byGetSpdDpx(byPhyPID);
                // get flow control
                pSPage_PortStatus->aSPortStatus[byPanelPortID].f2FlowCtrl = SWPORT_bGetFlowCtrlEn(byPhyPID);
            }
        }
    } // end for byPanelPortID
}