pisystem.c

vt6528芯片交换机API函数和文档运行程序

/*
 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
 * All rights reserved.
 *
 * This software is copyrighted by and is the sole property of
 * VIA Networking Technologies, Inc. This software may only be used
 * in accordance with the corresponding license agreement. Any unauthorized
 * use, duplication, transmission, distribution, or disclosure of this
 * software is expressly forbidden.
 *
 * This software is provided by VIA Networking Technologies, Inc. "as is"
 * and any express or implied warranties, including, but not limited to, the
 * implied warranties of merchantability and fitness for a particular purpose
 * are disclaimed. In no event shall VIA Networking Technologies, Inc.
 * be liable for any direct, indirect, incidental, special, exemplary, or
 * consequential damages.
 *
 *
 * File:    pisystem.c
 *
 * Purpose: System initialization/booting operations
 *
 * Author:  Tevin Chen
 *
 * Date:    Jan 08, 2002
 *
 * Functions:
 *
 * Revision History:
 *
 */


#if !defined(__PLATFORM_H__)
#include "platform.h"
#endif
#if !defined(__STR_H__)
#include "str.h"
#endif
#if !defined(__SOC_H__)
#include "soc.h"
#endif
#if !defined(__UART_H__)
#include "uart.h"
#endif
#if !defined(__TIMER_H__)
#include "timer.h"
#endif
#if !defined(__NVRAM_H__)
#include "nvram.h"
#endif
#include "tty.h"
#include "swmii.h"
#include "swsys.h"
#include "pieeprom.h"
#include "pigencfg.h"
#include "pimod.h"

#if !defined(__SWMODL_H__)
#include "swmodl.h"
#endif
#include "piport.h"
#include "piqos.h"
#include "pirate.h"
#include "swport.h"
#include "pisystem.h"

#ifdef __MODULE_WEB_SMART
#if !defined(__NETIF_H__)
#include "netif.h"
#endif
#include "piipcfg.h"
#include "swpkt.h"
#endif

#ifdef __PROV_MENU
#include "pistp.h"
#include "piipmmod.h"
#include "piprvmis.h"
#include "pi8021x.h"
#include "pigmrpmd.h"
#include "pismac.h"
#endif

#include "piaclgrp.h"

#include "pimacfltmd.h"


/*---------------------  Static Definitions  ------------------------*/
#define IRQ_TEST_LUCAS      1
#define AUTO_POLLING_WAIT   0x001FFFFF

/*---------------------  Static Types  ------------------------------*/

/*---------------------  Static Macros  -----------------------------*/

/*---------------------  Static Classes  ----------------------------*/

/*---------------------  Static Variables  --------------------------*/

/*---------------------  Static Functions  --------------------------*/
BOOL PISYS_bBoardDiag(void);

/*---------------------  Export Variables  --------------------------*/




void PISYS_vSetHwFromEep(UConfigBuf* pUCfgBuf)
{
    // init module cards
    PIMOD_vDetectModuleCard();

    // Setting trunk will update LogId list for port mapping
    PITRK_vSetHwFromEep((STrkPageCfg*)pUCfgBuf);

    PIPORT_vSetHwFromEep((SPortPageCfg*)pUCfgBuf);

    PIQOS_vSetHwFromEep((SQosPageCfg*)pUCfgBuf);

    PIRATE_vSetHwFromEep((SRatePageCfg*)pUCfgBuf);

    PIVLAN_vSetHwFromEep((SVlanPageCfg*)pUCfgBuf);
    PIVLNFLT_vSetHwFromEep((SVlanIngrFilterPageCfg*)pUCfgBuf);

    PIACL_vSetHwFromEep((SACLPageCfg *)pUCfgBuf);

    PIMISC_vSetHwFromEep((SMiscPageCfg*)pUCfgBuf);

    PISNF_vSetHwFromEep((SSniffPageCfg*)pUCfgBuf);

#ifdef __MODULE_WEB_SMART
    PIIPCONF_vSetHwFromEep();

    PIFWUPDT_vSetHwFromEep();
#endif

#ifdef __PROV_MENU

    PISTP_vSetHwFromEep((SSTPPageCfg*)pUCfgBuf);
    PIIGMP_vSetHwFromEep((SIGMPPageCfg*)pUCfgBuf);
    PI8021X_vSetHwFromEep((S8021XPageCfg*)pUCfgBuf);
    PISMAC_vSetHwFromEep((SSMacPageCfg*)pUCfgBuf);
    PIGMRP_vSetHwFromEep((SGMRPPageCfg*)pUCfgBuf);
    PIPROVMISC_vSetHwFromEep((SProvMiscPageCfg*)pUCfgBuf);

#endif

    PIMACFLT_vSetHwFromEep((SMacFltPageCfg *)pUCfgBuf);

}


void PISYS_vBoardWriteDefault(UConfigBuf* pUCfgBuf)
{
    // Clear nvram software cache
    STR_pvMemset(g_abyNVRSwCache, 0, NVR_SIZE_IPCONF + NVR_SIZE_FWUPDT + NVR_SW_CACHE_SIZE);

    PIEEP_vSetVerAndSig(TRUE);

    PIPORT_vSetEepDefault((SPortPageCfg*)pUCfgBuf, TRUE);

    PIQOS_vSetEepDefault((SQosPageCfg*)pUCfgBuf, TRUE);

    PIRATE_vSetEepDefault((SRatePageCfg*)pUCfgBuf, TRUE);

    PITRK_vSetEepDefault((STrkPageCfg*)pUCfgBuf, TRUE);

    PIVLAN_vSetEepDefault((SVlanPageCfg*)pUCfgBuf, TRUE);
    PIVLNFLT_vSetEepDefault((SVlanIngrFilterPageCfg*)pUCfgBuf, TRUE);

    PIACL_vSetEepDefault((SACLPageCfg*)pUCfgBuf, TRUE);

    PIMISC_vSetEepDefault((SMiscPageCfg*)pUCfgBuf, TRUE);

    PISNF_vSetEepDefault((SSniffPageCfg*)pUCfgBuf, TRUE);

    PIADM_vSetEepDefault(TRUE);

#ifdef __MODULE_WEB_SMART
    PIIPCONF_vSetEepDefault(TRUE);

    PIFWUPDT_vSetEepDefault(TRUE);
#endif

#ifdef __PROV_MENU

    PISTP_vSetEepDefault((SSTPPageCfg*)pUCfgBuf, TRUE);
    PIIGMP_vSetEepDefault((SIGMPPageCfg*)pUCfgBuf, TRUE);
    PI8021X_vSetEepDefault((S8021XPageCfg*) pUCfgBuf, TRUE);
    PISMAC_vSetEepDefault((SSMacPageCfg*) pUCfgBuf, TRUE);
    PIGMRP_vSetEepDefault((SGMRPPageCfg*) pUCfgBuf, TRUE);
    PIPROVMISC_vSetEepDefault((SProvMiscPageCfg*)pUCfgBuf, TRUE);

#endif
    PIMACFLT_vSetEepDefault((SMacFltPageCfg *)pUCfgBuf, TRUE);

    // write cache data into flash
    NVRAM_bWriteBlock(NVR_ADDR_IPCONF, g_abyNVRSwCache, (NVR_ADDR_DATA_AREA_START - NVR_ADDR_IPCONF) + EEP_SIZE_DATA_AREA, FALSE);
    NVRAM_vUpdateChecksum(EEP_SIZE_DATA_AREA);
    // write used data area size
    NVRAM_bWriteU32(NVR_ADDR_DATA_AREA_SIZE, (NVR_ADDR_DATA_AREA_START - NVR_ADDR_BASE) + EEP_SIZE_DATA_AREA);
}


void PISYS_vBoardBoot(void)
{
    UINT8   u8BaudRateMode;



    // init interrupt controller
    INTR_vInit();
    // CPU init misc setting
    SOC_vInit();
    // init timer, and hook ISR
    TMR_vInit();
    // init UART, and hook ISR
    UART_vInit();
    NVRAM_bReadU8(NVR_ADDR_UART_RATE_MODE, &u8BaudRateMode);
    UART_bSetBaudRate(u8BaudRateMode);

    // init target borad
    SWSYS_vBoardInit();
#ifdef __MODULE_WEB_SMART
    // Enable forwarding CPU packets.
    SWPKT_vDrvOpen();
#endif

    // Diagnose system
    while (!PISYS_bBoardDiag()) {
        TTY_vPutStr("\n\nThere may be some problems in your hardware.");
        TTY_vPutStr("\nPlease contact your manufacturer.");
        TTY_cGetChar();
    }

    // check eeprom checksum, version and signature
    TTY_vPutStr("\nEEPROM Content Check ...... ");
    if (!( PIEEP_bCheckVerAndSig() && NVRAM_bVerifyChecksum(EEP_SIZE_DATA_AREA) )) {
        TTY_vPutStr("FAIL");

        TTY_vPutStr("\n\nWriting default setting into EEPROM .. ");
        PISYS_vBoardWriteDefault(&g_UCfgBuf);
        TTY_vPutStr("OK");
    }
    else {
        TTY_vPutStr("PASS");
    }

    // Load eeprom config and set to hardware
    TTY_vPutStr("\n\nInitializing user configuration ... ");
    PISYS_vSetHwFromEep(&g_UCfgBuf);
    TTY_vPutStr("OK");

    INTR_vSwitchEnable();

/* //TOCHECK
    // Set giga 1 config from strapping
    if (SWPORT_bIsTbiPort(SWITCH_GIGA_PORT_ID_BASE))
        SWREG_vBitsOnU8(PHYCTL_MII_AUTOPOLL_CFG, MII_AUTOPOLL_GIGA0_TBI);

    // Set giga 2 config from strapping
    if (SWPORT_bIsTbiPort(SWITCH_GIGA_PORT_ID_BASE + 1))
        SWREG_vBitsOnU8(PHYCTL_MII_AUTOPOLL_CFG, MII_AUTOPOLL_GIGA1_TBI);
*/
}


BOOL PISYS_bBoardDiag(void)
{
    BOOL    bResult;
    UINT    uu;



    TTY_vPutStr("\n\nSystem Diagnosing:\n");

    TTY_vPutStr("\nSwitch Register R/W Test .. ");
    bResult = PISYS_bRegReadWriteTest();
    if (!bResult) {
        TTY_vPutStr("FAIL");
        return FALSE;
    }
    TTY_vPutStr("PASS");

    TTY_vPutStr("\nPhy Register R/W Test ..... ");
    for (uu = 0; uu < SWITCH_MEGA_PORT_NUM; uu++)
        bResult = bResult && PISYS_bMiiReadWriteTest(uu);
    if (!bResult) {
        TTY_vPutStr("FAIL");
        return FALSE;
    }
    TTY_vPutStr("PASS");

    return TRUE;
}


BOOL PISYS_bRegReadWriteTest(void)
{
    UINT8   byOrgVal;
    UINT8   byTmp;


    SWREG_vReadU8(FWDCTL_SWITCH_MAC_ADDR0 + 2, &byOrgVal);

    // Test pattern => 0x5A
    SWREG_vWriteU8(FWDCTL_SWITCH_MAC_ADDR0 + 2, 0x5A);
    SWREG_vReadU8(FWDCTL_SWITCH_MAC_ADDR0 + 2, &byTmp);
    if (byTmp != 0x5A)
        return FALSE;

    // restore to power-on default value
    SWREG_vWriteU8(FWDCTL_SWITCH_MAC_ADDR0 + 2, byOrgVal);

    return TRUE;
}


BOOL PISYS_bMiiReadWriteTest(UINT8 byPortId)
{
    UINT16  wOrgVal;
    UINT16  wTmp;

    
    // save original value
    SWMII_bReadU16(byPortId, MII_REG_ANAR, &wOrgVal);
    
    // Test pattern 1 => all tested bits are set to 1
    SWMII_bRegBitsOn(byPortId, MII_REG_ANAR, ANAR_ABL_MEGA);
    if (!SWMII_bIsRegBitsOn(byPortId, MII_REG_ANAR, ANAR_ABL_MEGA))
        return FALSE;

    // Test pattern 2 => all tested bits are set to 0
    SWMII_bRegBitsOff(byPortId, MII_REG_ANAR, ANAR_ABL_MEGA);
    if (!SWMII_bIsRegBitsOff(byPortId, MII_REG_ANAR, ANAR_ABL_MEGA))
        return FALSE;

    // restore to default value
    SWMII_bReadU16(byPortId, MII_REG_ANAR, &wTmp);
    wTmp &= (UINT16)~ANAR_ABL_MEGA;
    wOrgVal &= ANAR_ABL_MEGA;
    wTmp |= wOrgVal;
    SWMII_bWriteU16(byPortId, MII_REG_ANAR, wTmp);

    return TRUE;
}


BOOL PISYS_bNvramReadWriteTest(UINT32 u32EepBaseAddr)
{
    UINT8   byOrgVal, byTmp;
    BOOL    bResult = TRUE;


    // save original value
    NVRAM_bReadU8(u32EepBaseAddr,  &byOrgVal);

    // check result of test pattern
    NVRAM_bWriteU8(u32EepBaseAddr, 0x5A );
    NVRAM_bReadU8(u32EepBaseAddr, &byTmp);
    if (byTmp != 0x5A )
        bResult = FALSE;

    // restore to default value
    NVRAM_bWriteU8(u32EepBaseAddr, byOrgVal);
    return  bResult;
}


static void s_vAutoPollDelay(void)
{
    volatile UINT32     u32Delay;
    for (u32Delay = 0; u32Delay <= AUTO_POLLING_WAIT; u32Delay++)
    {
        
    }
    
}

BOOL PISYS_bIrqConnectTest(void)
{
    BOOL    bTestResult = TRUE;
    
    UINT32  dwIsrCnt;
    UINT32  ii;
    UINT16  wOrgSwitchIrq;


    // Backup irq status and open phy link status change irq only
    SWREG_vReadU16(CPUIF_IRQ_MASK, &wOrgSwitchIrq);
    SWREG_vWriteU16(CPUIF_IRQ_MASK, 0);

    // Keep original counter value of isr_lnkChg
    dwIsrCnt = g_SIsrCpuCntr.dwIsrLnkChg;

    // Clear link_change interrupt
    SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_LINK_CHG);

#if (IRQ_TEST_LUCAS)
    {
        
        UINT8   byPhyCtrlReg;
        
        
        /*
         * Step 1, Initialize port state, make sure port0 is LinkUp
         * If it is previously LoopBacked, turn off LoopBack,
         * and Set AutoPollling On, and wait for LinkUp.
         */
        SWMII_bRegBitsOn(0, MII_REG_BMCR, BMCR_RESET);  
        if (SWMII_bIsRegBitsOn(0, MII_REG_BMCR, BMCR_LBK))
        {     
            SWMII_bRegBitsOff(0, MII_REG_BMCR, BMCR_LBK);
        }
        
       SWMII_vSetAutoPollOn();       
       s_vAutoPollDelay();
       
        /*
         * Wait for LinkUp
         */
        for (ii = 0; ii < AUTO_POLLING_WAIT; ii++)
        {
            SWREG_vReadU8(PHYCTL_LINK_STATUS, &byPhyCtrlReg);   
            if (byPhyCtrlReg & 0x01) break;
        }
        
        if (ii == AUTO_POLLING_WAIT)
        {
            bTestResult = FALSE;
            goto exit;
        }
        
        /*
         * Step 2, Program Phy Reg Port0, Reg0 bit[14] = 1
         * LOOP_BACK_ENABLE
         */
        SWMII_bRegBitsOn(0, MII_REG_BMCR, BMCR_LBK);
         
         /*
          * Step 3, Enable Auto Polling
          */
        SWMII_vSetAutoPollOn();
        s_vAutoPollDelay();
        
        /*
         * Step 4, Check Link Change
         */         
        for (ii = 0; ii < AUTO_POLLING_WAIT; ii++)
        {
            SWREG_vReadU8(PHYCTL_LINK_STATUS_CHANGE, &byPhyCtrlReg);   
            if (byPhyCtrlReg & 0x01) break;
        }
        if (ii == AUTO_POLLING_WAIT)
        {            
            bTestResult = FALSE;
            goto exit;
        }
        
        /*
         * Check if CPU Interface signals IRQ
         */
        if (!SWREG_bWaitStatus(CPUIF_IRQ_STATUS, IRQ_STATUS_LINK_CHG, TRUE))
        {
            bTestResult = FALSE;
            goto exit;
        };
        
exit:
        /*
         * Disable LoopBack Mode
         */
        SWMII_vSetAutoPollOff();
        SWMII_bRegBitsOff(0, MII_REG_BMCR, BMCR_LBK);
            
    }
#else
    // wait for link_change
    for (ii = 0; ii < MAX_LOOP_TIMEOUT; ii++) {
        if (g_SIsrCpuCntr.dwIsrLnkChg > dwIsrCnt)
            break;
    }
#endif
    // If time out, return result is FALSE
    if (ii == MAX_LOOP_TIMEOUT)
        bTestResult = FALSE;

    // Write back the value of isr_phy
    g_SIsrCpuCntr.dwIsrLnkChg = dwIsrCnt;

    // Clear link_change interrupt
    SWREG_vWriteU16(CPUIF_IRQ_STATUS, IRQ_STATUS_LINK_CHG);

    // Restore org value of irq mask
    SWREG_vWriteU16(CPUIF_IRQ_MASK, wOrgSwitchIrq);
    
    return bTestResult;
}