cplb_tables.c

来自「快速开发基于Blackfin处理器的视频应用」· C语言 代码 · 共 115 行

/*****************************************************************************
Copyright(c) 2005 Analog Devices, Inc.  All Rights Reserved. This software is 
proprietary and confidential to Analog Devices, Inc. and its licensors.
******************************************************************************

$RCSfile: cplb_tables.c,v $
$Revision: 1.2 $
$Date: 2005/10/28 02:49:13 $

Project:	Developer Kit
Title:		cplb_tables
Author(s):	dwu
Revised by: 

Description:
			User defined CPLB tables for caching purposes.

References:
			None

******************************************************************************
Tab Setting:			4

Target Processor:		ADSP-BF533
Target Tools Revision:	ADSP VisualDSP++ v4.0.1.0 (Mar 18 2005 Update)
******************************************************************************

Modification History:
====================
$Log: cplb_tables.c,v $
Revision 1.2  2005/10/28 02:49:13  dwu
Added error checking code for JPEG/MJPEG routines, and added ADI
legal headers.

Revision 1.1.1.1  2005/10/13 02:50:16  dwu
no message

Revision 1.1  2005/07/29 06:28:03  dwu
Newly added files to contain project specific routines/data


*****************************************************************************/

#include "cplb_tables.h"
#include <cplb.h>


#define BIT9 (0x0200)			// workaround for anomaly 05000159/161
int codec_dcplbs_table[16][2] =	{
	// L1 DATA
	{ 0xFF800000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT | BIT9) },	// L1 Data A
	{ 0xFF900000,	(PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT | BIT9) },	// L1 Data B
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) },	// Standard Heap (index 0) NON Cached
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Slow Heap (index 1) Cached (USB buffer)

	// SDRAM bank 1
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory (YUV buffer decoder)
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_DNOCACHE | BIT9) },	// NON Cached Data Memory (YUV buffer encoder)
	
	// SDRAM bank 2
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Video Frame 0
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory

	// SDRAM bank 3
	{ 0x03000000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Video Frame 1
	{ 0x03400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) },	// Cached Data Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE | BIT9) },	// Async Memory Bank 0 (Prim A)
	{ 0x24000000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE | BIT9) },	// Async Memory Bank 1 (Prim B)
	{ 0x28000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 2 (Secnd)
	{ 0x2C000000,	(PAGE_SIZE_1MB | CPLB_DNOCACHE | BIT9) },	// Async Memory Bank 3

	// L2 memory
	{ 0xFEB00000,	(PAGE_SIZE_1MB | CPLB_DDOCACHE | BIT9) },	// 
	// other SDRAM .... . dummy entries
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_DDOCACHE | BIT9) }	//
};

int codec_icplbs_table[16][2] =	{
	// L1 CODE
	{ 0xFFA00000,	(PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT)	 },	// L1 Code
	
	// SDRAM bank 0
	{ 0x00000000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// dummy non cached instruction memory (keep free for data heap)
	{ 0x00400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// dummy non cached instruction memory (keep free for data heap)

	// SDRAM bank 1
	{ 0x01000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (YUV buffer decoder)
	{ 0x01400000,	(PAGE_SIZE_4MB | CPLB_INOCACHE) },	// NON Cached Instruction Memory (YUV buffer encoder)
	
	// SDRAM bank 2
	{ 0x02000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (Video Frame 0)
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// SDRAM bank 3
	{ 0x03000000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory (Video Frame 1)
	{ 0x03400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// Cached Instruction Memory

	// ASYNC MEMORY
	{ 0x20000000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// Async Memory Bank 0 (Prim A)
	{ 0x24000000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// Async Memory Bank 1 (Prim B)
	{ 0x28000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 2 (Second)
	{ 0x2C000000,	(PAGE_SIZE_1MB | CPLB_INOCACHE) },	// Async Memory Bank 3

	// L2 memory
	{ 0xFEB00000,	(PAGE_SIZE_1MB | CPLB_IDOCACHE) },	// 
	// other SDRAM .... . dummy entries
	{ 0x02400000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) },	// 
	{ 0x02800000,	(PAGE_SIZE_4MB | CPLB_IDOCACHE) }	//
};