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📄 sw_i2c_slave.s43

📁 MSP430和GPS的接口程序
💻 S43
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#include "sw_i2c_slave.h"

            NAME    Software_I2C

            PUBLIC  initSWI2C
            PUBLIC  resetSWI2C
            PUBLIC  regI2CCallBack
            PUBLIC  I2CEvent
            PUBLIC  I2CIdx
            PUBLIC  I2CRxBuff
            PUBLIC  I2CTxBuff
            PUBLIC  i2cIndex

;------------------------------------------------------------------------------
            RSEG    DATA16_C                ; Constant Data
;------------------------------------------------------------------------------
            EVEN                            ; Even alignment
                                            ;
SCL_AddrTbl                                 ; SCL receive address state table
            DW      Addr_1to9LH             ; SCL clk 1, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 1, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 2, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 2, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 3, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 3, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 4, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 4, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 5, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 5, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 6, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 6, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 7, 0->1 transition
            DW      Addr_1to7HL             ; SCL clk 7, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 8, 0->1 transition
            DW      Addr_8HL                ; SCL clk 8, 1->0 transition
            DW      Addr_1to9LH             ; SCL clk 9, 0->1 transition
            DW      Addr_9HL                ; SCL clk 9, 1->0 transition
                                            ;
SCL_RxTbl                                   ; SCL receive state table
            DW      Rx_1to9LH               ; SCL clk 1, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 1, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 2, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 2, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 3, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 3, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 4, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 4, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 5, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 5, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 6, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 6, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 7, 0->1 transition
            DW      Rx_1to7HL               ; SCL clk 7, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 8, 0->1 transition
            DW      Rx_8HL                  ; SCL clk 8, 1->0 transition
            DW      Rx_1to9LH               ; SCL clk 9, 0->1 transition
            DW      Rx_9HL                  ; SCL clk 9, 1->0 transition
                                            ;
SCL_TxTbl                                   ; SCL transmit state table
            DW      Tx_1to8LH               ; SCL clk 1, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 1, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 2, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 2, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 3, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 3, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 4, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 4, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 5, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 5, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 6, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 6, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 7, 0->1 transition
            DW      Tx_1to7HL               ; SCL clk 7, 1->0 transition
            DW      Tx_1to8LH               ; SCL clk 8, 0->1 transition
            DW      Tx_8HL                  ; SCL clk 8, 1->0 transition
            DW      Tx_9LH                  ; SCL clk 9, 0->1 transition
            DW      Tx_9HL                  ; SCL clk 9, 1->0 transition
                                            ;
SCL_NMATbl                                  ; SCL not my address state table
            DW      NMA_1to9LH              ; SCL clk 1, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 1, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 2, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 2, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 3, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 3, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 4, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 4, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 5, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 5, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 6, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 6, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 7, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 7, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 8, 0->1 transition
            DW      NMA_1to8HL              ; SCL clk 8, 1->0 transition
            DW      NMA_1to9LH              ; SCL clk 9, 0->1 transition
            DW      NMA_9HL                 ; SCL clk 9, 1->0 transition
                                            ;
;------------------------------------------------------------------------------
            RSEG    DATA16_N                ; Unintialized Data
;------------------------------------------------------------------------------
            EVEN                            ; Even alignment
                                            ;
I2CCBFunc   DS16    1                       ; I2C callback function
I2CIdx      DS16    1                       ; I2C buffer index
I2CRxBuff   DS      I2CRXBUFFLEN            ; I2C receive buffer
I2CTxBuff   DS      I2CTXBUFFLEN            ; I2C transmit buffer
I2CEvent    DS      1                       ; I2C event flag

i2cIndex    DS      1                       ; I2C state (for davinci_evm.c)

;------------------------------------------------------------------------------
            RSEG    CODE                    ; Program Code
;------------------------------------------------------------------------------
                                            ;
;------------------------------------------------------------------------------
initSWI2C   ; Initialize SW I2C
;------------------------------------------------------------------------------
            mov.w   #0,&I2CCBFunc           ; Clear callback function pointer
            bic.b   #SCL_PIN,&SCL_OUT       ; Set SCL output low
            call    #resetSWI2C             ; Reset I2C
            bis.b   #8,&P1DIR               ; Set debug pin as output  // MW Debug
            bic.b   #8,&P1OUT               ; Set debug low  // MW Debug
            ret                             ; Return from subroutine
                                            ;
;------------------------------------------------------------------------------
resetSWI2C  ; Reset SW I2C
;------------------------------------------------------------------------------
            clr.b   &I2CEvent               ; Clear I2C event flag
            clr.w   &I2CIdx                 ; Clear I2C state
            clr.b   I2C_DATA                ; Clear I2C_DATA register
            bic.b   #SDA_PIN,&SDA_DIR       ; Set SCL as input
            bic.b   #SDA_PIN,&SDA_DIR       ; Set SDA as input
            bic.b   #SDA_PIN,&SDA_OUT       ; Set SDA output low
            bic.b   #SCL_PIN,&SCL_IES       ; Set SCL for 0->1 interrupt edge
            bis.b   #SDA_PIN,&SDA_IES       ; Set SDA for 1->0 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            bis.b   #SCL_PIN,&SCL_IE        ; Enable SCL interrupt
            bic.b   #SDA_PIN,&SDA_IFG       ; Clear SDA interrupt flag
            bis.b   #SDA_PIN,&SDA_IE        ; Enable SDA interrupt
            ret                             ; Return from subroutine
                                            ;
;------------------------------------------------------------------------------
regI2CCallBack  ; Register SW I2C callback function
                ; R12 contains address of callback function
;------------------------------------------------------------------------------
            mov.w   R12,&I2CCBFunc          ; Register callback function
            ret                             ; Return from subroutine
                                            ;


;------------------------------------------------------------------------------
port1_ISR   ; Port 1 Interrupt Service Routine
            ; I2C SCL input triggers this ISR
;------------------------------------------------------------------------------
            br      @SCL_TBL+               ; Go to SCL state table entry
                                            ;
Addr_1to9LH                                 ; 0->1 edge for SCL clks 1 to 9
Rx_1to9LH                                   ; 0->1 edge for SCL clks 1 to 9
NMA_1to9LH                                  ; 0->1 edge for SCL clks 1 to 9
Tx_9LH                                      ; 0->1 edge for SCL clk 9
            mov.b   &SDA_IN,&SDA_IES        ; Set SDA interrupt edge
            bis.b   #SCL_PIN,&SCL_IES       ; Set SCL for 1->0 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            bic.b   #SDA_PIN,&SDA_IFG       ; Clear SDA interrupt flag
            bis.b   #SDA_PIN,&SDA_IE        ; Enable SDA interrupt
            reti                            ; Return from interrupt
                                            ;

Tx_1to8LH                                   ; 0->1 edge for SCL clks 1 to 8
            mov.b   &SDA_OUT,&SDA_IES       ; Set SDA edge interrupt direction
            bis.b   #SCL_PIN,&SCL_IES       ; Set SCL for 1->0 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            bic.b   #SDA_PIN,&SDA_IFG       ; Clear SDA interrupt flag
            bis.b   #SDA_PIN,&SDA_IE        ; Enable SDA interrupt
            reti                            ; Return from interrupt
                                            ;

Rx_8HL                                      ; 1->0 edge for SCL clk 8
            bis.b   #SDA_PIN,&SDA_DIR       ; Hold SDA low (set SDA as output)
Addr_1to7HL                                 ; 1->0 edge for SCL clks 1 to 7
Rx_1to7HL                                   ; 1->0 edge for SCL clks 1 to 7
            bic.b   #SCL_PIN,&SCL_IES       ; Set SCL for 0->1 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            bit.b   #SDA_PIN,&SDA_IES       ; SDA value saved in SDA_IES
            rlc.b   I2C_DATA                ; Left shift carry bit into I2C val
            bic.b   #SDA_PIN,&SDA_IE        ; Disable SDA interrupt
            reti                            ; Return from interrupt
                                            ;
NMA_1to8HL                                  ; 1->0 edge for SCL clks 1 to 8
            bic.b   #SCL_PIN,&SCL_IES       ; Set SCL for 0->1 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            bic.b   #SDA_PIN,&SDA_IE        ; Disable SDA interrupt
            reti                            ; Return from interrupt
                                            ;

Tx_1to7HL                                   ; 1->0 edge for SCL clks 1 to 7
            bic.b   #SCL_PIN,&SCL_IES       ; Set SCL for 0->1 interrupt edge
            bic.b   #SCL_PIN,&SCL_IFG       ; Clear SCL interrupt flag
            rla.b   I2C_DATA                ; Shift I2C data left

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