mv_regs.h

AMCC POWERPC 44X系列的U-BOOT文件

#define MV64360_CUNIT_DEBUG_HIGH				    0xf344
#define MV64360_CUNIT_MMASK					    0xf380

	/*  Cunit Base Address Enable Window Bits*/
#define MV64360_CUNIT_BASE_ADDR_WIN_0_BIT			 0x0
#define MV64360_CUNIT_BASE_ADDR_WIN_1_BIT			 0x1
#define MV64360_CUNIT_BASE_ADDR_WIN_2_BIT			 0x2
#define MV64360_CUNIT_BASE_ADDR_WIN_3_BIT			 0x3

	/*  MPSCs Clocks Routing Registers  */

#define MV64360_MPSC_ROUTING_REG				    0xb400
#define MV64360_MPSC_RX_CLOCK_ROUTING_REG			    0xb404
#define MV64360_MPSC_TX_CLOCK_ROUTING_REG			    0xb408

	/*  MPSCs Interrupts Registers	  */

#define MV64360_MPSC_CAUSE_REG(port)				   (0xb804 + (port<<3))
#define MV64360_MPSC_MASK_REG(port)				   (0xb884 + (port<<3))

#define MV64360_MPSC_MAIN_CONFIG_LOW(port)			   (0x8000 + (port<<12))
#define MV64360_MPSC_MAIN_CONFIG_HIGH(port)			   (0x8004 + (port<<12))
#define MV64360_MPSC_PROTOCOL_CONFIG(port)			   (0x8008 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG1(port)				   (0x800c + (port<<12))
#define MV64360_MPSC_CHANNEL_REG2(port)				   (0x8010 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG3(port)				   (0x8014 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG4(port)				   (0x8018 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG5(port)				   (0x801c + (port<<12))
#define MV64360_MPSC_CHANNEL_REG6(port)				   (0x8020 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG7(port)				   (0x8024 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG8(port)				   (0x8028 + (port<<12))
#define MV64360_MPSC_CHANNEL_REG9(port)				   (0x802c + (port<<12))
#define MV64360_MPSC_CHANNEL_REG10(port)			   (0x8030 + (port<<12))

	/*  MPSC0 Registers	 */


/***************************************/
/*	    SDMA Registers	       */
/***************************************/

#define MV64360_SDMA_CONFIG_REG(channel)			(0x4000 + (channel<<13))
#define MV64360_SDMA_COMMAND_REG(channel)			(0x4008 + (channel<<13))
#define MV64360_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel)	(0x4810 + (channel<<13))
#define MV64360_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel)	(0x4c10 + (channel<<13))
#define MV64360_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel)	(0x4c14 + (channel<<13))

#define MV64360_SDMA_CAUSE_REG					    0xb800
#define MV64360_SDMA_MASK_REG					    0xb880


/****************************************/
/* SDMA Address Space Targets		*/
/****************************************/

#define MV64360_SDMA_DRAM_CS_0_TARGET				    0x0e00
#define MV64360_SDMA_DRAM_CS_1_TARGET				    0x0d00
#define MV64360_SDMA_DRAM_CS_2_TARGET				    0x0b00
#define MV64360_SDMA_DRAM_CS_3_TARGET				    0x0700

#define MV64360_SDMA_DEV_CS_0_TARGET				    0x1e01
#define MV64360_SDMA_DEV_CS_1_TARGET				    0x1d01
#define MV64360_SDMA_DEV_CS_2_TARGET				    0x1b01
#define MV64360_SDMA_DEV_CS_3_TARGET				    0x1701

#define MV64360_SDMA_BOOT_CS_TARGET				    0x0f00

#define MV64360_SDMA_SRAM_TARGET				    0x0003
#define MV64360_SDMA_60X_BUS_TARGET				    0x4003

#define MV64360_PCI_0_TARGET					    0x0003
#define MV64360_PCI_1_TARGET					    0x0004


/* Devices BAR and size registers */

#define MV64360_DEV_CS0_BASE_ADDR				    0x028
#define MV64360_DEV_CS0_SIZE					    0x030
#define MV64360_DEV_CS1_BASE_ADDR				    0x228
#define MV64360_DEV_CS1_SIZE					    0x230
#define MV64360_DEV_CS2_BASE_ADDR				    0x248
#define MV64360_DEV_CS2_SIZE					    0x250
#define MV64360_DEV_CS3_BASE_ADDR				    0x038
#define MV64360_DEV_CS3_SIZE					    0x040
#define MV64360_BOOTCS_BASE_ADDR				    0x238
#define MV64360_BOOTCS_SIZE					    0x240

/* SDMA Window access protection */
#define MV64360_SDMA_WIN_ACCESS_NOT_ALLOWED 0
#define MV64360_SDMA_WIN_ACCESS_READ_ONLY 1
#define MV64360_SDMA_WIN_ACCESS_FULL 2

/* BRG Interrupts */

#define MV64360_BRG_CONFIG_REG(brg)				 (0xb200 + (brg<<3))
#define MV64360_BRG_BAUDE_TUNING_REG(brg)			 (0xb204 + (brg<<3))
#define MV64360_BRG_CAUSE_REG					    0xb834
#define MV64360_BRG_MASK_REG					    0xb8b4

/****************************************/
/* DMA Channel Control			*/
/****************************************/

#define MV64360_DMA_CHANNEL0_CONTROL				    0x840
#define MV64360_DMA_CHANNEL0_CONTROL_HIGH			    0x880
#define MV64360_DMA_CHANNEL1_CONTROL				    0x844
#define MV64360_DMA_CHANNEL1_CONTROL_HIGH			    0x884
#define MV64360_DMA_CHANNEL2_CONTROL				    0x848
#define MV64360_DMA_CHANNEL2_CONTROL_HIGH			    0x888
#define MV64360_DMA_CHANNEL3_CONTROL				    0x84C
#define MV64360_DMA_CHANNEL3_CONTROL_HIGH			    0x88C


/****************************************/
/*	     IDMA Registers		*/
/****************************************/

#define MV64360_DMA_CHANNEL0_BYTE_COUNT				    0x800
#define MV64360_DMA_CHANNEL1_BYTE_COUNT				    0x804
#define MV64360_DMA_CHANNEL2_BYTE_COUNT				    0x808
#define MV64360_DMA_CHANNEL3_BYTE_COUNT				    0x80C
#define MV64360_DMA_CHANNEL0_SOURCE_ADDR			    0x810
#define MV64360_DMA_CHANNEL1_SOURCE_ADDR			    0x814
#define MV64360_DMA_CHANNEL2_SOURCE_ADDR			    0x818
#define MV64360_DMA_CHANNEL3_SOURCE_ADDR			    0x81c
#define MV64360_DMA_CHANNEL0_DESTINATION_ADDR			    0x820
#define MV64360_DMA_CHANNEL1_DESTINATION_ADDR			    0x824
#define MV64360_DMA_CHANNEL2_DESTINATION_ADDR			    0x828
#define MV64360_DMA_CHANNEL3_DESTINATION_ADDR			    0x82C
#define MV64360_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER		    0x830
#define MV64360_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER		    0x834
#define MV64360_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER		    0x838
#define MV64360_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER		    0x83C
#define MV64360_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER		    0x870
#define MV64360_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER		    0x874
#define MV64360_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER		    0x878
#define MV64360_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER		    0x87C

 /*  IDMA Address Decoding Base Address Registers  */

#define MV64360_DMA_BASE_ADDR_REG0				    0xa00
#define MV64360_DMA_BASE_ADDR_REG1				    0xa08
#define MV64360_DMA_BASE_ADDR_REG2				    0xa10
#define MV64360_DMA_BASE_ADDR_REG3				    0xa18
#define MV64360_DMA_BASE_ADDR_REG4				    0xa20
#define MV64360_DMA_BASE_ADDR_REG5				    0xa28
#define MV64360_DMA_BASE_ADDR_REG6				    0xa30
#define MV64360_DMA_BASE_ADDR_REG7				    0xa38

 /*  IDMA Address Decoding Size Address Register   */

#define MV64360_DMA_SIZE_REG0					    0xa04
#define MV64360_DMA_SIZE_REG1					    0xa0c
#define MV64360_DMA_SIZE_REG2					    0xa14
#define MV64360_DMA_SIZE_REG3					    0xa1c
#define MV64360_DMA_SIZE_REG4					    0xa24
#define MV64360_DMA_SIZE_REG5					    0xa2c
#define MV64360_DMA_SIZE_REG6					    0xa34
#define MV64360_DMA_SIZE_REG7					    0xa3C

 /* IDMA Address Decoding High Address Remap and Access
		  Protection Registers			  */

#define MV64360_DMA_HIGH_ADDR_REMAP_REG0			    0xa60
#define MV64360_DMA_HIGH_ADDR_REMAP_REG1			    0xa64
#define MV64360_DMA_HIGH_ADDR_REMAP_REG2			    0xa68
#define MV64360_DMA_HIGH_ADDR_REMAP_REG3			    0xa6C
#define MV64360_DMA_BASE_ADDR_ENABLE_REG			    0xa80
#define MV64360_DMA_CHANNEL0_ACCESS_PROTECTION_REG		    0xa70
#define MV64360_DMA_CHANNEL1_ACCESS_PROTECTION_REG		    0xa74
#define MV64360_DMA_CHANNEL2_ACCESS_PROTECTION_REG		    0xa78
#define MV64360_DMA_CHANNEL3_ACCESS_PROTECTION_REG		    0xa7c
#define MV64360_DMA_ARBITER_CONTROL				    0x860
#define MV64360_DMA_CROSS_BAR_TIMEOUT				    0x8d0

 /*  IDMA Headers Retarget Registers   */

#define MV64360_DMA_HEADERS_RETARGET_CONTROL			    0xa84
#define MV64360_DMA_HEADERS_RETARGET_BASE			    0xa88

 /*  IDMA Interrupt Register  */

#define MV64360_DMA_INTERRUPT_CAUSE_REG				    0x8c0
#define MV64360_DMA_INTERRUPT_CAUSE_MASK			    0x8c4
#define MV64360_DMA_ERROR_ADDR					    0x8c8
#define MV64360_DMA_ERROR_SELECT				    0x8cc

 /*  IDMA Debug Register ( for internal use )	 */

#define MV64360_DMA_DEBUG_LOW					    0x8e0
#define MV64360_DMA_DEBUG_HIGH					    0x8e4
#define MV64360_DMA_SPARE					    0xA8C

/****************************************/
/* Timer_Counter			*/
/****************************************/

#define MV64360_TIMER_COUNTER0					    0x850
#define MV64360_TIMER_COUNTER1					    0x854
#define MV64360_TIMER_COUNTER2					    0x858
#define MV64360_TIMER_COUNTER3					    0x85C
#define MV64360_TIMER_COUNTER_0_3_CONTROL			    0x864
#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_CAUSE		    0x868
#define MV64360_TIMER_COUNTER_0_3_INTERRUPT_MASK		    0x86c

/****************************************/
/*	   Watchdog registers		*/
/****************************************/

#define MV64360_WATCHDOG_CONFIG_REG				    0xb410
#define MV64360_WATCHDOG_VALUE_REG				    0xb414

/****************************************/
/* I2C Registers			*/
/****************************************/

#define MV64360_I2C_SLAVE_ADDR					    0xc000
#define MV64360_I2C_EXTENDED_SLAVE_ADDR				    0xc010
#define MV64360_I2C_DATA					    0xc004
#define MV64360_I2C_CONTROL					    0xc008
#define MV64360_I2C_STATUS_BAUDE_RATE				    0xc00C
#define MV64360_I2C_SOFT_RESET					    0xc01c

/****************************************/
/* GPP Interface Registers		*/
/****************************************/

#define MV64360_GPP_IO_CONTROL					    0xf100
#define MV64360_GPP_LEVEL_CONTROL				    0xf110
#define MV64360_GPP_VALUE					    0xf104
#define MV64360_GPP_INTERRUPT_CAUSE				    0xf108
#define MV64360_GPP_INTERRUPT_MASK0				    0xf10c
#define MV64360_GPP_INTERRUPT_MASK1				    0xf114
#define MV64360_GPP_VALUE_SET					    0xf118
#define MV64360_GPP_VALUE_CLEAR					    0xf11c

/****************************************/
/* Interrupt Controller Registers	*/
/****************************************/

/****************************************/
/* Interrupts				*/
/****************************************/

#define MV64360_MAIN_INTERRUPT_CAUSE_LOW			    0x004
#define MV64360_MAIN_INTERRUPT_CAUSE_HIGH			    0x00c
#define MV64360_CPU_INTERRUPT0_MASK_LOW				    0x014
#define MV64360_CPU_INTERRUPT0_MASK_HIGH			    0x01c
#define MV64360_CPU_INTERRUPT0_SELECT_CAUSE			    0x024
#define MV64360_CPU_INTERRUPT1_MASK_LOW				    0x034
#define MV64360_CPU_INTERRUPT1_MASK_HIGH			    0x03c
#define MV64360_CPU_INTERRUPT1_SELECT_CAUSE			    0x044
#define MV64360_INTERRUPT0_MASK_0_LOW				    0x054
#define MV64360_INTERRUPT0_MASK_0_HIGH				    0x05c
#define MV64360_INTERRUPT0_SELECT_CAUSE				    0x064
#define MV64360_INTERRUPT1_MASK_0_LOW				    0x074
#define MV64360_INTERRUPT1_MASK_0_HIGH				    0x07c
#define MV64360_INTERRUPT1_SELECT_CAUSE				    0x084

/****************************************/
/*	MPP Interface Registers		*/
/****************************************/

#define MV64360_MPP_CONTROL0					    0xf000
#define MV64360_MPP_CONTROL1					    0xf004
#define MV64360_MPP_CONTROL2					    0xf008
#define MV64360_MPP_CONTROL3					    0xf00c

/****************************************/
/*    Serial Initialization registers	*/
/****************************************/

#define MV64360_SERIAL_INIT_LAST_DATA				    0xf324
#define MV64360_SERIAL_INIT_CONTROL				    0xf328
#define MV64360_SERIAL_INIT_STATUS				    0xf32c


#endif /* __INCgt64360rh */