cpci405.c

AMCC POWERPC 44X系列的U-BOOT文件

		 */
		if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
			bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
			sprintf(str, "%ld.%ld.%ld.%ld",
				(bd->bi_ip_addr & 0xff000000) >> 24,
				(bd->bi_ip_addr & 0x00ff0000) >> 16,
				(bd->bi_ip_addr & 0x0000ff00) >> 8,
				(bd->bi_ip_addr & 0x000000ff));
			setenv("ipaddr", str);
		}
	}
#endif

	if (cpci405_version() >= 2) {
		puts("\n*** U-Boot Version does not match Board Version!\n");
		puts("*** CPCI-405 Board Version 2.x detected!\n");
		puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n");
	}

#endif /* CONFIG_CPCI405_VER2 */

	/*
	 * Select cts (and not dsr) on uart1
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | 0x00001000);

	return (0);
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
#ifndef CONFIG_CPCI405_VER2
	int index;
	int len;
#endif
	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));
	unsigned short ver;

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming CPCI405");
	} else {
		puts(str);
	}

	ver = cpci405_version();
	printf(" (Ver %d.x, ", ver);

#if 0 /* test-only */
	if (ver >= 2) {
		volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;

		if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
			puts ("FLASH Bank B, ");
		} else {
			puts ("FLASH Bank A, ");
		}
	}
#endif

	if (ctermm2()) {
		char str[4];

		/*
		 * Read board-id and save in env-variable
		 */
		sprintf(str, "%d", *(unsigned char *)0xf0000400);
		setenv("boardid", str);
		printf("CTERM-M2 - Id=%s)", str);
	} else {
		if (cpci405_host()) {
			puts ("PCI Host Version)");
		} else {
			puts ("PCI Adapter Version)");
		}
	}

#ifndef CONFIG_CPCI405_VER2
	puts ("\nFPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = fpgadata[index];
		printf("%s ", &(fpgadata[index+1]));
		index += len+3;
	}
#endif

	putc ('\n');

	/*
	 * Disable sleep mode in LXT971
	 */
	lxt971_no_sleep();

	return 0;
}

/* ------------------------------------------------------------------------- */

long int initdram (int board_type)
{
	unsigned long val;

	mtdcr(memcfga, mem_mb0cf);
	val = mfdcr(memcfgd);

#if 0
	printf("\nmb0cf=%x\n", val); /* test-only */
	printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif

	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}

/* ------------------------------------------------------------------------- */

int testdram (void)
{
	/* TODO: XXX XXX XXX */
	printf ("test: 16 MB - ok\n");

	return (0);
}

/* ------------------------------------------------------------------------- */

#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET

void ide_set_reset(int on)
{
	volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;

	/*
	 * Assert or deassert CompactFlash Reset Pin
	 */
	if (on) {		/* assert RESET */
		*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
	} else {		/* release RESET */
		*fpga_mode |= CFG_FPGA_MODE_CF_RESET;
	}
}

#endif /* CONFIG_IDE_RESET */
#endif /* CONFIG_CPCI405_VER2 */


#ifdef CONFIG_CPCI405AB

#define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
			  |= CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_SET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
			  &= ~CFG_FPGA_MODE_1WIRE_DIR)
#define ONE_WIRE_GET     (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
			  & CFG_FPGA_MODE_1WIRE)

/*
 * Generate a 1-wire reset, return 1 if no presence detect was found,
 * return 0 otherwise.
 * (NOTE: Does not handle alarm presence from DS2404/DS1994)
 */
int OWTouchReset(void)
{
	int result;

	ONE_WIRE_CLEAR;
	udelay(480);
	ONE_WIRE_SET;
	udelay(70);

	result = ONE_WIRE_GET;

	udelay(410);
	return result;
}


/*
 * Send 1 a 1-wire write bit.
 * Provide 10us recovery time.
 */
void OWWriteBit(int bit)
{
	if (bit) {
		/*
		 * write '1' bit
		 */
		ONE_WIRE_CLEAR;
		udelay(6);
		ONE_WIRE_SET;
		udelay(64);
	} else {
		/*
		 * write '0' bit
		 */
		ONE_WIRE_CLEAR;
		udelay(60);
		ONE_WIRE_SET;
		udelay(10);
	}
}


/*
 * Read a bit from the 1-wire bus and return it.
 * Provide 10us recovery time.
 */
int OWReadBit(void)
{
	int result;

	ONE_WIRE_CLEAR;
	udelay(6);
	ONE_WIRE_SET;
	udelay(9);

	result = ONE_WIRE_GET;

	udelay(55);
	return result;
}


void OWWriteByte(int data)
{
	int loop;

	for (loop=0; loop<8; loop++) {
		OWWriteBit(data & 0x01);
		data >>= 1;
	}
}


int OWReadByte(void)
{
	int loop, result = 0;

	for (loop=0; loop<8; loop++) {
		result >>= 1;
		if (OWReadBit()) {
			result |= 0x80;
		}
	}

	return result;
}


int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	volatile unsigned short val;
	int result;
	int i;
	unsigned char ow_id[6];
	char str[32];
	unsigned char ow_crc;

	/*
	 * Clear 1-wire bit (open drain with pull-up)
	 */
	val = *(volatile unsigned short *)0xf0400000;
	val &= ~0x1000; /* clear 1-wire bit */
	*(volatile unsigned short *)0xf0400000 = val;

	result = OWTouchReset();
	if (result != 0) {
		puts("No 1-wire device detected!\n");
	}

	OWWriteByte(0x33); /* send read rom command */
	OWReadByte(); /* skip family code ( == 0x01) */
	for (i=0; i<6; i++) {
		ow_id[i] = OWReadByte();
	}
	ow_crc = OWReadByte(); /* read crc */

	sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]);
	printf("Setting environment variable 'ow_id' to %s\n", str);
	setenv("ow_id", str);

	return 0;
}
U_BOOT_CMD(
	onewire,	1,	1,	do_onewire,
	"onewire - Read 1-write ID\n",
	NULL
	);


#define CFG_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
#define CFG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/

/*
 * Write backplane ip-address...
 */
int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	bd_t *bd = gd->bd;
	char *buf;
	ulong crc;
	char str[32];
	char *ptr;
	IPaddr_t ipaddr;

	buf = malloc(CFG_ENV_SIZE_2);
	if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
		puts("\nError reading backplane EEPROM!\n");
	} else {
		crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
		if (crc != *(ulong *)buf) {
			printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
			return -1;
		}

		/*
		 * Find bp_ip
		 */
		ptr = strstr(buf+4, "bp_ip=");
		if (ptr == NULL) {
			printf("ERROR: bp_ip not found!\n");
			return -1;
		}
		ptr += 6;
		ipaddr = string_to_ip(ptr);

		/*
		 * Update whole ip-addr
		 */
		bd->bi_ip_addr = ipaddr;
		sprintf(str, "%ld.%ld.%ld.%ld",
			(bd->bi_ip_addr & 0xff000000) >> 24,
			(bd->bi_ip_addr & 0x00ff0000) >> 16,
			(bd->bi_ip_addr & 0x0000ff00) >> 8,
			(bd->bi_ip_addr & 0x000000ff));
		setenv("ipaddr", str);
		printf("Updated ip_addr from bp_eeprom to %s!\n", str);
	}

	free(buf);

	return 0;
}
U_BOOT_CMD(
	getbpip,	1,	1,	do_get_bpip,
	"getbpip - Update IP-Address with Backplane IP-Address\n",
	NULL
	);

/*
 * Set and print backplane ip...
 */
int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	char *buf;
	char str[32];
	ulong crc;

	if (argc < 2) {
		puts("ERROR!\n");
		return -1;
	}

	printf("Setting bp_ip to %s\n", argv[1]);
	buf = malloc(CFG_ENV_SIZE_2);
	memset(buf, 0, CFG_ENV_SIZE_2);
	sprintf(str, "bp_ip=%s", argv[1]);
	strcpy(buf+4, str);
	crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
	*(ulong *)buf = crc;

	if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
		puts("\nError writing backplane EEPROM!\n");
	}

	free(buf);

	return 0;
}
U_BOOT_CMD(
	setbpip,	2,	1,	do_set_bpip,
	"setbpip - Write Backplane IP-Address\n",
	NULL
	);

#endif /* CONFIG_CPCI405AB */