ixethnpe.h

AMCC POWERPC 44X系列的U-BOOT文件

 * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK
 *
 * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message.
 */
#define IX_ETHNPE_PC_SETAPMACTABLE_ACK              0x11

/**
 * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK
 *
 * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message.
 */
#define IX_ETHNPE_SETLOOPBACK_MODE_ACK              (0x12)

/*--------------------------------------------------------------------------
 * Queue Manager Queue entry bit field boundary definitions
 *------------------------------------------------------------------------*/

/**
 * @def MASK(hi,lo)
 *
 * @brief Macro for mask
 */
#define MASK(hi,lo)                    (((1 << (1 + ((hi) - (lo)))) - 1) << (lo))

/**
 * @def BITS(x,hi,lo)
 *
 * @brief Macro for bits
 */
#define BITS(x,hi,lo)                  (((x) & MASK(hi,lo)) >> (lo))

/**
 * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK
 *
 * @brief QMgr Queue LENGTH field mask
 */
#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK   0x3fff

/**
 * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R
 *
 * @brief QMgr Queue FLAG field right boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_FLAG_R             20

/**
 * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK
 *
 * @brief QMgr Queue FLAG field mask
 *
 * Multicast bit : BIT(4)
 * Broadcast bit : BIT(5)
 * IP bit        : BIT(6) (linux only)
 *
 */
#ifdef __vxworks
#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x30
#else
#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK           0x70
#endif


/**
 * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L
 *
 * @brief QMgr Queue NPE ID field left boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_NPEID_L            1

/**
 * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R
 *
 * @brief QMgr Queue NPE ID field right boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_NPEID_R            0

/**
 * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L
 *
 * @brief QMgr Queue Priority field left boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L            2

/**
 * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R
 *
 * @brief QMgr Queue Priority field right boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R            0

/**
 * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L 
 *
 * @brief QMgr Queue Address field left boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_ADDR_L             31

/**
 * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R
 *
 * @brief QMgr Queue Address field right boundary
 */
#define IX_ETHNPE_QM_Q_FIELD_ADDR_R              5

/*--------------------------------------------------------------------------
 * Queue Manager Queue entry bit field masks
 *------------------------------------------------------------------------*/

/**
 * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK 
 *
 * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)

/**
 * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK  
 *
 * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)

/**
 * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK 
 *
 * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK
 *
 * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
                  IX_ETHNPE_QM_Q_FIELD_PRIOR_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK 
 *
 * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK 
 *
 * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry
 */
#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
                  IX_ETHNPE_QM_Q_FIELD_NPEID_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK 
 * 
 * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager 
 * Entry
 */
#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \
            MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \
                  IX_ETHNPE_QM_Q_FIELD_ADDR_R)

/*--------------------------------------------------------------------------
 * Queue Manager Queue entry bit field value extraction macros
 *------------------------------------------------------------------------*/

/**
 * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x)
 *
 * @brief Extraction macro for Address field of FreeNet Queue Manager Entry 
 *
 * Pointer to an mbuf buffer descriptor
 */
#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \
            ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK)

/**
 * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x)
 *
 * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry 
 *
 * Set to 0 for entries originating from the Eth0 NPE; 
 * Set to 1 for entries originating from the Eth1 NPE.
 */
#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \
            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)

/**
 * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x)
 *
 * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry 
 *
 * 0-5: Assignable (by the XScale client) to any of the physical ports.
 * 6: It is reserved
 * 7: Indication that the NPE did not find the associated frame's destination MAC address within 
 * its internal filtering database.
 */
#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \
            BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \
                     IX_ETHNPE_QM_Q_Field_PortID_R)

/**
 * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x)
 *
 * @brief Extraction macro for Address field of RxEnet Queue Manager Entry
 *
 * Pointer to an mbuf buffer descriptor
 */
#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \
            ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK)

/**
 * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x)
 *
 * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry
 *
 * Priority of the packet (as described in IEEE 802.1D). This field is
 * cleared upon return from the Ethernet NPE to the TxEnetDone queue.
 */
#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \
            BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \
                     IX_ETHNPE_QM_Q_FIELD_PRIOR_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x)
 *
 * @brief Extraction macro for Address field of Queue Manager TxEnet Queue 
 * Manager Entry
 *
 * Pointer to an mbuf buffer descriptor
 */
#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \
            ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK)

/**
 * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x)
 *
 * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry
 *
 * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries 
 * originating from the Eth1 NPE.
 */
#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \
            BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \
                     IX_ETHNPE_QM_Q_FIELD_NPEID_R)

/**
 * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x)
 *
 * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry
 *
 * Pointer to an mbuf buffer descriptor
 */
#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \
            ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK)


/*--------------------------------------------------------------------------
 * NPE limits
 *------------------------------------------------------------------------*/

/**
 * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN
 * 
 * @brief Macro to check the minimum length of a rx free buffer
 */
#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64)

/**
 * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
 * 
 * @brief Mask to apply to the mbuf length before submitting it to the NPE
 * (the NPE handles only rx free mbufs which are multiple of 64)
 * 
 * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK
 */
#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63)

/**
 * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size)
 * 
 * @brief  Round up to get the size necessary to receive without chaining
 * the frames which are (size) bytes (the NPE operates by multiple of 64)
 * e.g. To receive 1514 bytes frames, the size of the buffers in replenish
 * has to be at least (1514+63)&(~63) = 1536 bytes.
 *
 */
#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63)

/**
 * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size)
 *
 * @brief Round down to apply to the mbuf length before submitting
 * it to the NPE. (the NPE operates by multiple of 64)
 *
 */
#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63)

/**
 * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX
 * 
 * @brief maximum mbuf length supported by the NPE
 * 
 * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX
 */
#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320)

/**
 * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
 * 
 * @brief default mbuf length supported by the NPE
 * 
 * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT
 */
#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522)

/**
 * @def IX_ETHNPE_ACC_LENGTH_OFFSET
 *
 * @brief Offset of the cluster length field in the word shared with the NPEs
 */
#define IX_ETHNPE_ACC_LENGTH_OFFSET 16

/**
 * @def IX_ETHNPE_ACC_PKTLENGTH_MASK
 *
 * @brief Mask of the cluster length field in the word shared with the NPEs
 */
#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff


/**
 *@}
 */

#endif /* __doxygen_HIDE */