ixnpea.h

AMCC POWERPC 44X系列的U-BOOT文件

#ifndef __doxygen_HIDE  /* This file is not part of the API */

/**
 * @file    IxNpeA.h
 *
 * @date    22-Mar-2002
 *
 * @brief   Header file for the IXP400 ATM NPE API
 *
 * 
 * @par
 * IXP400 SW Release version 2.0
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * @par
 * -- End of Copyright Notice --
 */

/**
 * @defgroup IxNpeA IXP400 NPE-A (IxNpeA) API
 *
 * @brief The Public API for the IXP400 NPE-A
 *
 * @{
 */

#ifndef IX_NPE_A_H
#define IX_NPE_A_H

#include "IxQMgr.h"
#include "IxOsal.h"
#include "IxQueueAssignments.h"

/* General Message Ids */

/* ATM Message Ids */

/**
 * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE
 *
 * @brief ATM Message ID command to write the data to the offset in the
 * Utopia Configuration Table
 */
#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_WRITE       0x20

/**
 * @def IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD
 *
 * @brief ATM Message ID command triggers the NPE to copy the Utopia
 * Configuration Table to the Utopia coprocessor
 */
#define IX_NPE_A_MSSG_ATM_UTOPIA_CONFIG_LOAD        0x21

/**
 * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD
 *
 * @brief ATM Message ID command triggers the NPE to read-back the Utopia
 * status registers and update the Utopia Status Table.
 */
#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_UPLOAD      0x22

/**
 * @def IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ
 *
 * @brief ATM Message ID command to read the Utopia Status Table at the
 * specified offset.
 */
#define IX_NPE_A_MSSG_ATM_UTOPIA_STATUS_READ        0x23

/**
 * @def IX_NPE_A_MSSG_ATM_TX_ENABLE
 *
 * @brief ATM Message ID command triggers the NPE to re-enable processing
 * of any entries on the TxVcQ for this port.
 *
 * This command will be ignored for a port already enabled
 */
#define IX_NPE_A_MSSG_ATM_TX_ENABLE                 0x25

 /**
 * @def IX_NPE_A_MSSG_ATM_TX_DISABLE
 *
 * @brief ATM Message ID command triggers the NPE to disable processing on
 * this port
 *
 * This command will be ignored for a port already disabled
 */
#define IX_NPE_A_MSSG_ATM_TX_DISABLE                0x26

/**
 * @def IX_NPE_A_MSSG_ATM_RX_ENABLE
 *
 * @brief ATM Message ID command triggers the NPE to process any received
 * cells for this VC according to the VC Lookup Table.
 *
 * Re-issuing this command with different contents for a VC that is not
 * disabled will cause unpredictable behavior.
 */
#define IX_NPE_A_MSSG_ATM_RX_ENABLE                 0x27

/**
 * @def IX_NPE_A_MSSG_ATM_RX_DISABLE
 *
 * @brief ATM Message ID command triggers the NPE to disable processing for
 * this VC.
 *
 * This command will be ignored for a VC already disabled
 */
#define IX_NPE_A_MSSG_ATM_RX_DISABLE                0x28

/**
 * @def IX_NPE_A_MSSG_ATM_STATUS_READ
 *
 * @brief ATM Message ID command to read the ATM status. The data is returned via
 * a response message
 */
#define IX_NPE_A_MSSG_ATM_STATUS_READ               0x29

/*--------------------------------------------------------------------------
 * HSS Message IDs
 *--------------------------------------------------------------------------*/

/**
 * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE
 *
 * @brief HSS Message ID command writes the ConfigWord value to the location
 * in the HSS_CONFIG_TABLE specified by offset for HSS port hPort.
 */
#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_WRITE         0x40

/**
 * @def IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD
 *
 * @brief HSS Message ID command triggers the NPE to copy the contents of the
 * HSS Configuration Table to the appropriate configuration registers in the
 * HSS coprocessor for the port specified by hPort.
 */
#define IX_NPE_A_MSSG_HSS_PORT_CONFIG_LOAD          0x41

/**
 * @def IX_NPE_A_MSSG_HSS_PORT_ERROR_READ
 *
 * @brief HSS Message ID command triggers the NPE to return an HssErrorReadResponse
 * message for HSS port hPort.
 */
#define IX_NPE_A_MSSG_HSS_PORT_ERROR_READ           0x42

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE
 *
 * @brief HSS Message ID command triggers the NPE to reset internal status and
 * enable the HssChannelized operation on the HSS port specified by hPort.
 */
#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_ENABLE          0x43

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE
 *
 * @brief HSS Message ID command triggers the NPE to disable the HssChannelized
 * operation on the HSS port specified by hPort.
 */
#define IX_NPE_A_MSSG_HSS_CHAN_FLOW_DISABLE         0x44

/**
 * @def  IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE
 *
 * @brief HSS Message ID command writes the HSSnC_IDLE_PATTERN value for HSS
 * port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_IDLE_PATTERN_WRITE   0x45

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE
 *
 * @brief HSS Message ID command writes the HSSnC_NUM_CHANNELS value for HSS
 * port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_NUM_CHANS_WRITE      0x46

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE
 *
 * @brief HSS Message ID command writes the HSSnC_RX_BUF_ADDR value for HSS
 * port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_ADDR_WRITE    0x47

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE
 *
 * @brief HSS Message ID command  writes the HSSnC_RX_BUF_SIZEB and
 * HSSnC_RX_TRIG_PERIOD values for HSS port hPort.  (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_RX_BUF_CFG_WRITE     0x48

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE
 *
 * @brief HSS Message ID command writes the HSSnC_TX_BLK1_SIZEB,
 * HSSnC_TX_BLK1_SIZEW, HSSnC_TX_BLK2_SIZEB, and HSSnC_TX_BLK2_SIZEW  values
 * for HSS port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BLK_CFG_WRITE     0x49

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE
 * @brief HSS Message ID command writes the HSSnC_TX_BUF_ADDR value for HSS
 * port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_ADDR_WRITE    0x4A

/**
 * @def IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE
 *
 * @brief HSS Message ID command writes the HSSnC_TX_BUF_SIZEN value for HSS
 * port hPort. (n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_CHAN_TX_BUF_SIZE_WRITE    0x4B

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE
 *
 * @brief HSS Message ID command triggers the NPE to reset internal status and
 * enable the HssPacketized operation for the flow specified by pPipe on
 * the HSS port specified by hPort.
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_ENABLE      0x50

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE
 * @brief HSS Message ID command triggers the NPE to disable the HssPacketized
 * operation for the flow specified by pPipe on the HSS port specified by hPort.
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FLOW_DISABLE     0x51

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE
 * @brief HSS Message ID command writes the HSSnP_NUM_PIPES value for HSS
 * port hPort.(n=hPort)
 */
#define IX_NPE_A_MSSG_HSS_PKT_NUM_PIPES_WRITE       0x52

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE
 *
 * @brief HSS Message ID command writes the HSSnP_PIPEp_FIFOSIZEW value for
 * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_FIFO_SIZEW_WRITE 0x53

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE
 *
 * @brief HSS Message ID command writes the HSSnP_PIPEp_HDLC_RXCFG and
 * HSSnP_PIPEp_HDLC_TXCFG values for packet-pipe pPipe on HSS port hPort.
 * (n=hPort, p=pPipe)
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_HDLC_CFG_WRITE   0x54

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE
 *
 * @brief HSS Message ID command writes the HSSnP_PIPEp_IDLE_PATTERN value
 * for packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_IDLE_PATTERN_WRITE 0x55

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE
 *
 * @brief HSS Message ID command writes the HSSnP_PIPEp_RXSIZEB value for
 * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_RX_SIZE_WRITE    0x56

/**
 * @def IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE
 *
 * @brief HSS Message ID command writes the HSSnP_PIPEp_MODE value for
 * packet-pipe pPipe on HSS port hPort.  (n=hPort, p=pPipe)
 */
#define IX_NPE_A_MSSG_HSS_PKT_PIPE_MODE_WRITE       0x57



/* Queue Entry Masks */

/*--------------------------------------------------------------------------
 *  ATM Descriptor Structure offsets
 *--------------------------------------------------------------------------*/

/**
 * @def IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Status field
 *
 * It is used for descriptor error reporting.
 */
#define IX_NPE_A_RXDESCRIPTOR_STATUS_OFFSET          0

/**
 * @def IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor VC ID field
 *
 * It is used to hold an identifier number for this VC
 */
#define IX_NPE_A_RXDESCRIPTOR_VCID_OFFSET            1

/**
 * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Current Mbuf
 * Size field
 *
 * Number of bytes the current mbuf data buffer can hold
 */
#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFSIZE_OFFSET    2

/**
 * @def IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor ATM Header
 */
#define IX_NPE_A_RXDESCRIPTOR_ATMHEADER_OFFSET       4

/**
 * @def IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf length
 *
 *
 * RX - Initialized to zero.  The NPE updates this field as each cell is received and
 * zeroes it with every new mbuf for chaining. Will not be bigger than currBbufSize.
 */
#define IX_NPE_A_RXDESCRIPTOR_CURRMBUFLEN_OFFSET    12

/**
 * @def IX_NPE_A_RXDESCRIPTOR_TIMELIMIT__OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Time Limit field
 *
 * Contains the Payload Reassembly Time Limit (used for aal0_xx only)
 */
#define IX_NPE_A_RXDESCRIPTOR_TIMELIMIT_OFFSET        14

/**
 * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
 *
 * The current mbuf pointer of a chain of mbufs.
 */
#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFF_OFFSET     20

/**
 * @def IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET
 *
 * @brief ATM Descriptor structure offset for Receive Descriptor Current MBuf Pointer
 *
 * Pointer to the next byte to be read or next free location to be written.