def_lpblackfin.h

AMCC POWERPC 44X系列的U-BOOT文件

/*
 * def_LPBlackfin.h
 *
 * This file is subject to the terms and conditions of the GNU Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Non-GPL License also available as part of VisualDSP++
 *
 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
 *
 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
 *
 * This file under source code control, please send bugs or changes to:
 * [e-mail]
 *
 */

/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */

#ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H

/*
 * #if !defined(__ADSPLPBLACKFIN__)
 * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
 * #endif
 */

#define MK_BMSK_( x ) (1<<x)	/* Make a bit mask from a bit position */

/*
 * System Register Bits
 */

/*
 * ASTAT register
 */

/* definitions of ASTAT bit positions */
#define ASTAT_AZ_P		0x00000000	/* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN_P		0x00000001	/* Result of last ALU0 or shifter operation is negative */
#define ASTAT_CC_P		0x00000005	/* Condition Code, used for holding comparison results */
#define ASTAT_AQ_P		0x00000006	/* Quotient Bit */
#define ASTAT_RND_MOD_P		0x00000008	/* Rounding mode, set for biased, clear for unbiased */
#define ASTAT_AC0_P		0x0000000C	/* Result of last ALU0 operation generated a carry */
#define ASTAT_AC0_COPY_P	0x00000002	/* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1_P		0x0000000D	/* Result of last ALU1 operation generated a carry */
#define ASTAT_AV0_P		0x00000010	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV0S_P		0x00000011	/* Sticky version of ASTAT_AV0  */
#define ASTAT_AV1_P		0x00000012	/* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_AV1S_P		0x00000013	/* Sticky version of ASTAT_AV1  */
#define ASTAT_V_P		0x00000018	/* Result of last ALU0 or MAC0 operation overflowed */
#define ASTAT_V_COPY_P		0x00000003	/* Result of last ALU0 or MAC0 operation overflowed */
#define ASTAT_VS_P		0x00000019	/* Sticky version of ASTAT_V */

/* ** Masks */
#define ASTAT_AZ		MK_BMSK_(ASTAT_AZ_P)	/* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN		MK_BMSK_(ASTAT_AN_P)	/* Result of last ALU0 or shifter operation is negative */
#define ASTAT_AC0		MK_BMSK_(ASTAT_AC0_P)	/* Result of last ALU0 operation generated a carry */
#define ASTAT_AC0_COPY		MK_BMSK_(ASTAT_AC0_COPY_P)	/* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1		MK_BMSK_(ASTAT_AC1_P)	/* Result of last ALU0 operation generated a carry */
#define ASTAT_AV0		MK_BMSK_(ASTAT_AV0_P)	/* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV1		MK_BMSK_(ASTAT_AV1_P)	/* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_CC		MK_BMSK_(ASTAT_CC_P)	/* Condition Code, used for holding comparison results */
#define ASTAT_AQ		MK_BMSK_(ASTAT_AQ_P)	/* Quotient Bit */
#define ASTAT_RND_MOD		MK_BMSK_(ASTAT_RND_MOD_P)	/* Rounding mode, set for biased, clear for unbiased */
#define ASTAT_V			MK_BMSK_(ASTAT_V_P)	/* Overflow Bit */
#define ASTAT_V_COPY		MK_BMSK_(ASTAT_V_COPY_P)	/* Overflow Bit */

/*
 * SEQSTAT register
 */

/* ** Bit Positions */
#define SEQSTAT_EXCAUSE0_P	0x00000000	/* Last exception cause bit 0 */
#define SEQSTAT_EXCAUSE1_P	0x00000001	/* Last exception cause bit 1 */
#define SEQSTAT_EXCAUSE2_P	0x00000002	/* Last exception cause bit 2 */
#define SEQSTAT_EXCAUSE3_P	0x00000003	/* Last exception cause bit 3 */
#define SEQSTAT_EXCAUSE4_P	0x00000004	/* Last exception cause bit 4 */
#define SEQSTAT_EXCAUSE5_P	0x00000005	/* Last exception cause bit 5 */
#define SEQSTAT_IDLE_REQ_P	0x0000000C	/* Pending idle mode request, set by IDLE instruction */
#define SEQSTAT_SFTRESET_P	0x0000000D	/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_HWERRCAUSE0_P	0x0000000E	/* Last hw error cause bit 0 */
#define SEQSTAT_HWERRCAUSE1_P	0x0000000F	/* Last hw error cause bit 1 */
#define SEQSTAT_HWERRCAUSE2_P	0x00000010	/* Last hw error cause bit 2 */
#define SEQSTAT_HWERRCAUSE3_P	0x00000011	/* Last hw error cause bit 3 */
#define SEQSTAT_HWERRCAUSE4_P	0x00000012	/* Last hw error cause bit 4 */
#define SEQSTAT_HWERRCAUSE5_P	0x00000013	/* Last hw error cause bit 5 */
#define SEQSTAT_HWERRCAUSE6_P	0x00000014	/* Last hw error cause bit 6 */
#define SEQSTAT_HWERRCAUSE7_P	0x00000015	/* Last hw error cause bit 7 */

/* ** Masks */
/* Exception cause */
#define SEQSTAT_EXCAUSE		MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
				MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
				MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
				MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
				MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
				MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
				0

/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET	MK_BMSK_(SEQSTAT_SFTRESET_P )

/* Last hw error cause */
#define SEQSTAT_HWERRCAUSE	MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
				MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
				MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
				MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
				MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
				0

/*
 * SYSCFG register
 */

/* ** Bit Positions */
#define SYSCFG_SSSTEP_P		0x00000000	/* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN_P		0x00000001	/* Enable cycle counter (=1) */
#define SYSCFG_SNEN_P		0x00000002	/* Self nesting Interrupt Enable */

/* ** Masks */
#define SYSCFG_SSSTEP		MK_BMSK_(SYSCFG_SSSTEP_P)	/* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN		MK_BMSK_(SYSCFG_CCEN_P)		/* Enable cycle counter (=1) */
#define SYSCFG_SNEN		MK_BMSK_(SYSCFG_SNEN_P		/* Self Nesting Interrupt Enable */

/* Backward-compatibility for typos in prior releases */
#define SYSCFG_SSSSTEP		SYSCFG_SSSTEP
#define SYSCFG_CCCEN		SYSCFG_CCEN

/*
 * Core MMR Register Map
 */

/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
#define SRAM_BASE_ADDRESS	0xFFE00000	/* SRAM Base Address Register */
#define DMEM_CONTROL		0xFFE00004	/* Data memory control */
#define DCPLB_STATUS		0xFFE00008	/* Data Cache Programmable Look-Aside Buffer Status */
#define DCPLB_FAULT_STATUS	0xFFE00008	/* "" (older define) */
#define DCPLB_FAULT_ADDR	0xFFE0000C	/* Data Cache Programmable Look-Aside Buffer Fault Address */
#define DCPLB_ADDR0		0xFFE00100	/* Data Cache Protection Lookaside Buffer 0 */
#define DCPLB_ADDR1		0xFFE00104	/* Data Cache Protection Lookaside Buffer 1 */
#define DCPLB_ADDR2		0xFFE00108	/* Data Cache Protection Lookaside Buffer 2 */
#define DCPLB_ADDR3		0xFFE0010C	/* Data Cacheability Protection Lookaside Buffer 3 */
#define DCPLB_ADDR4		0xFFE00110	/* Data Cacheability Protection Lookaside Buffer 4 */
#define DCPLB_ADDR5		0xFFE00114	/* Data Cacheability Protection Lookaside Buffer 5 */
#define DCPLB_ADDR6		0xFFE00118	/* Data Cacheability Protection Lookaside Buffer 6 */
#define DCPLB_ADDR7		0xFFE0011C	/* Data Cacheability Protection Lookaside Buffer 7 */
#define DCPLB_ADDR8		0xFFE00120	/* Data Cacheability Protection Lookaside Buffer 8 */
#define DCPLB_ADDR9		0xFFE00124	/* Data Cacheability Protection Lookaside Buffer 9 */
#define DCPLB_ADDR10		0xFFE00128	/* Data Cacheability Protection Lookaside Buffer 10 */
#define DCPLB_ADDR11		0xFFE0012C	/* Data Cacheability Protection Lookaside Buffer 11 */
#define DCPLB_ADDR12		0xFFE00130	/* Data Cacheability Protection Lookaside Buffer 12 */
#define DCPLB_ADDR13		0xFFE00134	/* Data Cacheability Protection Lookaside Buffer 13 */
#define DCPLB_ADDR14		0xFFE00138	/* Data Cacheability Protection Lookaside Buffer 14 */
#define DCPLB_ADDR15		0xFFE0013C	/* Data Cacheability Protection Lookaside Buffer 15 */
#define DCPLB_DATA0		0xFFE00200	/* Data Cache 0 Status */
#define DCPLB_DATA1		0xFFE00204	/* Data Cache 1 Status */
#define DCPLB_DATA2		0xFFE00208	/* Data Cache 2 Status */
#define DCPLB_DATA3		0xFFE0020C	/* Data Cache 3 Status */
#define DCPLB_DATA4		0xFFE00210	/* Data Cache 4 Status */
#define DCPLB_DATA5		0xFFE00214	/* Data Cache 5 Status */
#define DCPLB_DATA6		0xFFE00218	/* Data Cache 6 Status */
#define DCPLB_DATA7		0xFFE0021C	/* Data Cache 7 Status */
#define DCPLB_DATA8		0xFFE00220	/* Data Cache 8 Status */
#define DCPLB_DATA9		0xFFE00224	/* Data Cache 9 Status */
#define DCPLB_DATA10		0xFFE00228	/* Data Cache 10 Status */
#define DCPLB_DATA11		0xFFE0022C	/* Data Cache 11 Status */
#define DCPLB_DATA12		0xFFE00230	/* Data Cache 12 Status */
#define DCPLB_DATA13		0xFFE00234	/* Data Cache 13 Status */
#define DCPLB_DATA14		0xFFE00238	/* Data Cache 14 Status */
#define DCPLB_DATA15		0xFFE0023C	/* Data Cache 15 Status */
#define DTEST_COMMAND		0xFFE00300	/* Data Test Command Register */
#define DTEST_DATA0		0xFFE00400	/* Data Test Data Register */
#define DTEST_DATA1		0xFFE00404	/* Data Test Data Register */

/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
#define IMEM_CONTROL		0xFFE01004	/* Instruction Memory Control */
#define ICPLB_STATUS		0xFFE01008	/* Instruction Cache miss status */
#define CODE_FAULT_STATUS	0xFFE01008	/* "" (older define) */
#define ICPLB_FAULT_ADDR	0xFFE0100C	/* Instruction Cache miss address */
#define CODE_FAULT_ADDR		0xFFE0100C	/* "" (older define) */
#define ICPLB_ADDR0		0xFFE01100	/* Instruction Cacheability Protection Lookaside Buffer 0 */
#define ICPLB_ADDR1		0xFFE01104	/* Instruction Cacheability Protection Lookaside Buffer 1 */
#define ICPLB_ADDR2		0xFFE01108	/* Instruction Cacheability Protection Lookaside Buffer 2 */
#define ICPLB_ADDR3		0xFFE0110C	/* Instruction Cacheability Protection Lookaside Buffer 3 */
#define ICPLB_ADDR4		0xFFE01110	/* Instruction Cacheability Protection Lookaside Buffer 4 */
#define ICPLB_ADDR5		0xFFE01114	/* Instruction Cacheability Protection Lookaside Buffer 5 */
#define ICPLB_ADDR6		0xFFE01118	/* Instruction Cacheability Protection Lookaside Buffer 6 */
#define ICPLB_ADDR7		0xFFE0111C	/* Instruction Cacheability Protection Lookaside Buffer 7 */
#define ICPLB_ADDR8		0xFFE01120	/* Instruction Cacheability Protection Lookaside Buffer 8 */
#define ICPLB_ADDR9		0xFFE01124	/* Instruction Cacheability Protection Lookaside Buffer 9 */
#define ICPLB_ADDR10		0xFFE01128	/* Instruction Cacheability Protection Lookaside Buffer 10 */
#define ICPLB_ADDR11		0xFFE0112C	/* Instruction Cacheability Protection Lookaside Buffer 11 */
#define ICPLB_ADDR12		0xFFE01130	/* Instruction Cacheability Protection Lookaside Buffer 12 */
#define ICPLB_ADDR13		0xFFE01134	/* Instruction Cacheability Protection Lookaside Buffer 13 */
#define ICPLB_ADDR14		0xFFE01138	/* Instruction Cacheability Protection Lookaside Buffer 14 */
#define ICPLB_ADDR15		0xFFE0113C	/* Instruction Cacheability Protection Lookaside Buffer 15 */
#define ICPLB_DATA0		0xFFE01200	/* Instruction Cache 0 Status */
#define ICPLB_DATA1		0xFFE01204	/* Instruction Cache 1 Status */
#define ICPLB_DATA2		0xFFE01208	/* Instruction Cache 2 Status */
#define ICPLB_DATA3		0xFFE0120C	/* Instruction Cache 3 Status */
#define ICPLB_DATA4		0xFFE01210	/* Instruction Cache 4 Status */
#define ICPLB_DATA5		0xFFE01214	/* Instruction Cache 5 Status */
#define ICPLB_DATA6		0xFFE01218	/* Instruction Cache 6 Status */
#define ICPLB_DATA7		0xFFE0121C	/* Instruction Cache 7 Status */
#define ICPLB_DATA8		0xFFE01220	/* Instruction Cache 8 Status */
#define ICPLB_DATA9		0xFFE01224	/* Instruction Cache 9 Status */
#define ICPLB_DATA10		0xFFE01228	/* Instruction Cache 10 Status */
#define ICPLB_DATA11		0xFFE0122C	/* Instruction Cache 11 Status */
#define ICPLB_DATA12		0xFFE01230	/* Instruction Cache 12 Status */
#define ICPLB_DATA13		0xFFE01234	/* Instruction Cache 13 Status */
#define ICPLB_DATA14		0xFFE01238	/* Instruction Cache 14 Status */
#define ICPLB_DATA15		0xFFE0123C	/* Instruction Cache 15 Status */
#define ITEST_COMMAND		0xFFE01300	/* Instruction Test Command Register */
#define ITEST_DATA0		0xFFE01400	/* Instruction Test Data Register */
#define ITEST_DATA1		0xFFE01404	/* Instruction Test Data Register */

/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
#define EVT0			0xFFE02000	/* Event Vector 0 ESR Address */
#define EVT1			0xFFE02004	/* Event Vector 1 ESR Address */
#define EVT2			0xFFE02008	/* Event Vector 2 ESR Address */