abl_arm922t_cp15_driver.c

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

    {
        MRC     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0;
    }
#endif

#ifdef __ICCARM__
    /* use IAR CC intrinsic function to read CP15 reg */
  	mmu_reg = __MRC(15, 0, 1, 0, 0); 
#endif


    return ((mmu_reg & _BIT(0)) == _BIT(0));
}

/***********************************************************************
 *
 * Function: cp15_get_mmu_control_reg
 *
 * Purpose:
 *  To return the current value of  the MMU Coprocessor (CP15) Control
 *  register.
 *
 * Processing:
 *  Fetch the MMU control register to a variable and return it
 *
 * Parameters: None
 *
 * Outputs: None
 *
 * Returns: 
 *  The current value of the MMU Control register (cp15) as an UNS_32
 *
 * Notes: None
 *
 **********************************************************************/
UNS_32 cp15_get_mmu_control_reg(void)
{
    register UNS_32 mmu_reg;

#ifdef __GNUC__
    asm ("MRC p15, 0, %0, c1, c0, 0" : "=r" (mmu_reg));
#endif

#ifdef __ghs__
    mmu_reg = getstatus ();

#endif
#ifdef __arm
    __asm
    {
        MRC     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0;
    }
#endif
#ifdef __ICCARM__
    /* use IAR CC intrinsic function to read CP15 reg */
  	mmu_reg = __MRC(15, 0, 1, 0, 0); 
#endif

    return (mmu_reg);
}

/***********************************************************************
 *
 * Function: cp15_set_mmu_control_reg
 *
 * Purpose:
 *  To set MMU Coprocessor (CP15) Control register.
 *
 * Processing:
 *  Set the MMU control register to a value passed as parameter.
 *
 * Parameters: 
 *  mmu_reg - The value to be set in the MMU Control register (cp15). 
 *
 * Outputs: None
 *
 * Returns: None
 *
 * Notes: None
 *
 **********************************************************************/
void cp15_set_mmu_control_reg(UNS_32 mmu_reg)
{
#ifdef __GNUC__
    asm ("MCR p15, 0, %0, c1, c0, 0" : "=r" (mmu_reg));
#endif

#ifdef __ghs__
    set_mmu(mmu_reg);
#endif

#ifdef __arm
    __asm
    {
        MCR     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0 
    }
#endif
#ifdef __ICCARM__
     
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)mmu_reg, 1, 0, 0);
#endif
}

/***********************************************************************
 *
 * Function: cp15_set_mmu
 *
 * Purpose:
 *  To enable or disable the MMU as specified.
 *
 * Processing:
 *  Fetch the MMU control register to a variable. If the argument passed
 *  is true, set the MMU enable bit, otherwise, clear it. Write the
 *  resultant value back to the control register.
 *
 * Parameters: 
 *  enable - TRUE if the MMU must be enabled
 *           FALSE if the MMU must be disabled
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: None
 *
 **********************************************************************/
void cp15_set_mmu (BOOL_32 enable)
{
    register UNS_32 mmu_reg;
    
    /* Read-Modify-Write the MMU register */
    mmu_reg = cp15_get_mmu_control_reg();
    
    if (enable)
    {
        mmu_reg |= ARM922T_MMU_CONTROL_M;
    }
    else
    {
        mmu_reg &= ~ARM922T_MMU_CONTROL_M;
    }
    
#ifdef __GNUC__
    asm ("MCR p15, 0, %0, c1, c0, 0" : "=r" (mmu_reg));
#endif

#ifdef __ghs__
    set_mmu(mmu_reg);
#endif

#ifdef __arm
    __asm
    {
        MCR     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0 
    }
#endif
#ifdef __ICCARM__
     
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)mmu_reg, 1, 0, 0);
#endif

}

/***********************************************************************
 *
 * Function: cp15_invalidate_cache
 *
 * Purpose:
 *  Invalidates the Instruction and Data caches
 *
 * Processing:
 *  Use the ARM instruction to unconditionally invalidate the entire 
 *  cache.
 *
 * Parameters: None
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: 
 *  This function invalidates all cache data including dirty data (data
 *  that has been modified in cache but not yet written to main memory).
 *  Use with caution. See ARM922T TRM.
 *
 **********************************************************************/
void cp15_invalidate_cache (void)
{
#ifdef __GNUC__
    // Invalidate both I- and D-cache completely
    asm ("MOV r0, #0");
    asm ("MCR p15, 0, r0, c7, c7, 0");
#endif
#ifdef __ghs__
    inval_all_cache ();
#endif

#ifdef __arm
    __asm
    {
        MOV     r0, 0
        MCR     p15, 0, r0, c7, c7, 0
    }
#endif
#ifdef __ICCARM__
    {
        register UNS_32 temp = 0;

        /* Use IAR intrinsic functions */
        __MCR(15, 0, (UNS_32)temp, 7, 7, 0);
    }
#endif
}

/***********************************************************************
 *
 * Function: cp15_invalidate_tlb
 *
 * Purpose:
 *  Invalidates the Translation Lookaside Buffers
 *
 * Processing:
 *  Use the ARM instruction to unconditionally invalidate the I- and D-
 *  TLBs.
 *
 * Parameters: None
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: 
 *  See the ARM922T TRM.
 *
 **********************************************************************/
void cp15_invalidate_tlb (void)
{
#ifdef __GNUC__
    asm ("MOV r0, #0");
    asm ("MCR p15, 0, r0, c8, c7, 0");
    asm ("NOP");
    asm ("NOP");
    asm ("NOP");
#endif
#ifdef __ghs__
    inval_all_tlb ();
#endif

#ifdef __arm
    __asm
    {
        MOV     r0, 0
        // Invalidate TLBs
        MCR      p15, 0, r0, ARM922T_MMU_REG_TLB_OPS, c7, 0
        NOP
        NOP
        NOP
    }
#endif
#ifdef __ICCARM__
    {
        register UNS_32 temp = 0;

        /* Use IAR intrinsic functions */
        __MCR(15, 0, (UNS_32)temp, 8, 7, 0);
        __no_operation();
        __no_operation();
        __no_operation();
    }
#endif
}

/***********************************************************************
 *
 * Function: cp15_set_transtable_base
 *
 * Purpose:
 *  Sets the first-level translation table base address
 *
 * Processing:
 *  Masks out the lower 12 bits of the address passed. Writes register
 *  2 of CP15 with the base address passed as parameter.
 *
 * Parameters: 
 *  addr - Translation table base address
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: 
 *  The address must be aligned on a 16K boundary. See ARM922T TRM.
 *
 **********************************************************************/
void cp15_set_transtable_base (UNS_32 addr)
{
    addr &= 0xFFFFC000;
    
#ifdef __GNUC__
    asm ("MCR p15, 0, %0, c2, c0, 0": "=r" (addr));
#endif

#ifdef __ghs__
    set_ttb(addr);       
#endif

#ifdef __arm
    __asm
    {
        MCR     p15, 0, addr, ARM922T_MMU_REG_TTB, c0, 0
    }
#endif

#ifdef __ICCARM__
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)addr, 2, 0, 0);
#endif
}

/***********************************************************************
 *
 * Function: cp15_set_icache
 *
 * Purpose:
 *  Enables or disables the instruction cache
 *
 * Processing:
 *  Fetch the MMU control register to a variable. If the argument passed
 *  is true, set the I-cache enable bit, otherwise, clear it. Write the
 *  resultant value back to the control register.
 *
 * Parameters:
 *  enable - TRUE if the I-cache must be enabled
 *           FALSE if the I-cache must be disabled
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: None
 *
 **********************************************************************/
void cp15_set_icache (BOOL_32 enable)
{
    UNS_32 mmu_reg;
    
    mmu_reg = cp15_get_mmu_control_reg();
    
    if (enable)
        mmu_reg |= ARM922T_MMU_CONTROL_I;
    else
        mmu_reg &= ~ARM922T_MMU_CONTROL_I;

#ifdef __GNUC__
    asm ("MCR p15, 0, %0, c1, c0, 0" : "=r" (mmu_reg));
#endif

#ifdef __ghs__
    set_mmu(mmu_reg);
#endif

#ifdef __arm
    __asm
    {
        MCR     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0 
    }
#endif
#ifdef __ICCARM__
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)mmu_reg, 1, 0, 0);
#endif
}

/***********************************************************************
 *
 * Function: cp15_set_dcache
 *
 * Purpose:
 *  Enables or disables the data cache
 *
 * Processing:
 *  Fetch the MMU control register to a variable. If the argument passed
 *  is true, set the D-cache enable bit, otherwise, clear it. Write the
 *  resultant value back to the control register.
 *
 * Parameters:
 *  enable - TRUE if the D-cache must be enabled
 *           FALSE if the D-cache must be disabled
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes: None
 *
 **********************************************************************/
void cp15_set_dcache (BOOL_32 enable)
{
    UNS_32 mmu_reg;
    
    mmu_reg = cp15_get_mmu_control_reg();
    
    if (enable)
        mmu_reg |= ARM922T_MMU_CONTROL_C;
    else
        mmu_reg &= ~ARM922T_MMU_CONTROL_C;

#ifdef __GNUC__
    asm ("MCR p15, 0, %0, c1, c0, 0" : "=r" (mmu_reg));
#endif

#ifdef __ghs__
    set_mmu(mmu_reg);
#endif

#ifdef __arm
    __asm
    {
        MCR     p15, 0, mmu_reg, ARM922T_MMU_REG_CONTROL, c0, 0 
    }
#endif
#ifdef __ICCARM__
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)mmu_reg, 1, 0, 0);
#endif
}

/***********************************************************************
 *
 * Function: cp15_set_domain_access
 *
 * Purpose:
 *  Define the access permissions for the 16 MMU domains.
 *
 * Processing:
 *  Use the ARM instruction to write the value passed as argument to 
 *  the domain access control regsiter.
 *
 * Parameters:
 *  dac - 32-bit value encoded as follows:
 *
 *   31  29  27  25  23  21  19  17  15  13  11  9 8 7 6 5 4 3 2 1 0 
 *   ---------------------------------------------------------------
 *  |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
 *   ---------------------------------------------------------------
 *   For each domain (2 bits), 
 *     00 - No access
 *     01 - Client
 *     10 - Reserved (same as no access)
 *     11 - Manager
 *
 * Outputs: None
 *
 * Returns: Nothing
 *
 * Notes:
 *  See the ARM922T TRM.
 *
 **********************************************************************/
void cp15_set_domain_access (UNS_32 dac)
{
#ifdef __GNUC__        
        asm ("MCR p15, 0, %0, c3, c0, 0" : "=r" (dac));
#endif
#ifdef __ghs__
        set_dac(dac);
#endif

#ifdef __arm
        __asm
        {
            MCR     p15, 0, dac, ARM922T_MMU_REG_DAC, c0, 0
        }
#endif
#ifdef __ICCARM__
    /* Use IAR intrinsic functions */
    __MCR(15, 0, (UNS_32)dac, 3, 0, 0);
#endif
}