📄 abl_irq_fiq.h
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/***********************************************************************
* $Workfile: abl_irq_fiq.h $
* $Revision: 1.3 $
* $Author: WellsK $
* $Date: Apr 15 2004 15:18:46 $
*
* Project: ARM core interrupt functions
*
* Description:
* This file contains the function declarations for routines for
* enabling, disabling and restoring the state of IRQ and FIQ
* exceptions.
*
* Revision History:
* $Log: //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/abl/include/abl_irq_fiq.h-arc $
*
* Rev 1.3 Apr 15 2004 15:18:46 WellsK
* Added IAR intrinsic functions for inline assembly.
*
* Rev 1.2 Apr 14 2004 09:29:14 WellsK
* Suppressed missing return statement warnings for inline
* assembly code with IAR toolchains.
*
* Rev 1.1 Mar 29 2004 12:10:18 WellsK
* Added support for IAR toolchain.
*
* Rev 1.0 Jun 09 2003 12:03:04 WellsK
* Initial revision.
*
*
***********************************************************************
* SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
* OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
* AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
* SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
*
* SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
* FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
* SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
* FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
*
* COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
* CAMAS, WA
**********************************************************************/
#ifndef ABL_IRQ_FIQ_H
#define ABL_IRQ_FIQ_H
#ifdef __GNUC__
static __inline UNS_32 disable_irq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"ORR %1, %0, #0x80" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 disable_fiq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"ORR %1, %0, #0x40" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 disable_irq_fiq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"ORR %1, %0, #0xC0" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 enable_irq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"BIC %1, %0, #0x80" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 enable_fiq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"BIC %1, %0, #0x40" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 enable_irq_fiq(void)
{
register UNS_32 ret, tmp;
asm
(
"MRS %0, CPSR" "\n\t"
"BIC %1, %0, #0xC0" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
);
return ret;
}
static __inline UNS_32 disable_irq_fiq_mask(UNS_32 mask)
{
register UNS_32 ret, tmp;
asm
(
"BIC %1, %2, #0x2F" "\n\t"
"MRS %0, CPSR" "\n\t"
"ORR %1, %0, %1" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
: "r" (mask)
);
return ret;
}
static __inline UNS_32 enable_irq_fiq_mask(UNS_32 mask)
{
register UNS_32 ret, tmp;
asm
(
"BIC %1, %2, #0x2F" "\n\t"
"MRS %0, CPSR" "\n\t"
"BIC %1, %0, %1" "\n\t"
"MSR CPSR_c, %1" "\n\t"
: "=r" (ret), "=r" (tmp)
: "r" (mask)
);
return ret;
}
static __inline UNS_32 restore_exceptions(UNS_32 old)
{
register UNS_32 ret, tmp, tmp2;
asm
(
"BIC %1, %3, #0x2F" "\n\t"
"MRS %0, CPSR" "\n\t"
"BIC %2, %0, #0xC0" "\n\t"
"ORR %2, %2, %1" "\n\t"
"MSR CPSR_c, %2" "\n\t"
: "=r" (ret), "=r" (tmp), "=r" (tmp2)
: "r" (old)
);
return ret;
}
#endif /* __GNUC__ */
#ifdef __ghs__
__asm UNS_32 disable_irq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
ORR r1, r0, #0x80
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 disable_fiq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
ORR r1, r0, #0x40
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 disable_irq_fiq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
ORR r1, r0, #0xC0
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 enable_irq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
bic r1, r0, #0x80
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 enable_fiq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
bic r1, r0, #0x40
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 enable_irq_fiq(void)
{
STMFD [sp]!, {r1}
MRS r0, CPSR
bic r1, r0, #0xC0
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
}
__asm UNS_32 disable_irq_fiq_mask(UNS_32 mask)
{
%reg mask
STMFD [sp]!, {r1}
BIC r1, mask, #0x2F
MRS r0, CPSR
ORR r1, r0, r1
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
%con mask
STMFD [sp]!, {r1}
MOV r1, mask
BIC r1, r1, #0x2F
MRS r0, CPSR
ORR r1, r0, r1
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
%error
}
__asm UNS_32 enable_irq_fiq_mask(UNS_32 mask)
{
%reg mask
STMFD [sp]!, {r1}
BIC r1, mask, #0x2F
MRS r0, CPSR
BIC r1, r0, r1
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
%con mask
STMFD [sp]!, {r1}
MOV r1, mask
BIC r1, r1, #0x2F
MRS r0, CPSR
BIC r1, r0, r1
MSR CPSR_c, r1
LDMFD [sp]!, {r1}
%error
}
__asm UNS_32 restore_exceptions(UNS_32 old)
{
%reg old
STMFD [sp]!, {r1-r2}
BIC r1, old, #0x2F
MRS r0, CPSR
BIC r2, r0, #0xC0
ORR r2, r2, r1
MSR CPSR_c, r2
LDMFD [sp]!, {r1-r2}
%con old
STMFD [sp]!, {r1-r2}
MOV r1, old
BIC r1, r1, #0x2F
MRS r0, CPSR
BIC r2, r0, #0xC0
ORR r2, r2, r1
MSR CPSR_c, r2
LDMFD [sp]!, {r1-r2}
%error
}
#endif /* GHS */
#ifdef __arm
static __inline UNS_32 disable_irq(void)
{
register UNS_32 ret;
__asm
{
mrs ret ,CPSR;
orr r1, ret, #0x80;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 disable_fiq(void)
{
register UNS_32 ret;
__asm
{
mrs ret, CPSR;
orr r1, ret, #0x40;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 disable_irq_fiq(void)
{
register UNS_32 ret;
__asm
{
mrs ret, CPSR;
orr r1, ret, #0xc0;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 enable_irq(void)
{
register UNS_32 ret;
__asm
{
mrs ret, CPSR;
bic r1, ret, #0x80;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 enable_fiq(void)
{
register UNS_32 ret;
__asm
{
mrs ret, CPSR;
bic r1, ret, #0x40;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 enable_irq_fiq(void)
{
register UNS_32 ret;
__asm
{
mrs ret, CPSR;
bic r1, ret, #0xc0;
msr CPSR_c, r1
}
return ret;
}
static __inline UNS_32 disable_irq_fiq_mask(UNS_32 mask)
{
register UNS_32 ret;
__asm
{
bic r1, mask, #0x2f;
mrs ret, CPSR;
orr r2, ret, r1;
msr CPSR_c, r2
}
return ret;
}
static __inline UNS_32 enable_irq_fiq_mask(UNS_32 mask)
{
register UNS_32 ret;
__asm
{
bic r1, mask, #0x2f;
mrs ret, CPSR;
bic r2, ret, r1;
msr CPSR_c, r2
}
return ret;
}
static __inline UNS_32 restore_exceptions(UNS_32 old)
{
register UNS_32 ret;
__asm
{
bic r1, old, #0x2f;
mrs ret, CPSR;
bic r2, ret, #0xc0;
orr r3, r2, r1;
msr CPSR_c, r3
}
return ret;
}
#endif /* __arm */
/* IAR CC uses R0 for single input argument to function.
Return value is also R0 */
#ifdef __ICCARM__
#include "inarm.h"
#pragma inline
static UNS_32 disable_irq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr | 0x80);
return c_cpsr;
}
#pragma inline
static UNS_32 disable_fiq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr | 0x40);
return c_cpsr;
}
#pragma inline
static UNS_32 disable_irq_fiq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr | 0xC0);
return c_cpsr;
}
#pragma inline
static UNS_32 enable_irq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr & ~0x80);
return c_cpsr;
}
#pragma inline
static UNS_32 enable_fiq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr & ~0x40);
return c_cpsr;
}
#pragma inline
static UNS_32 enable_irq_fiq(void)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR(c_cpsr & ~0xC0);
return c_cpsr;
}
#pragma inline
static UNS_32 disable_irq_fiq_mask(UNS_32 mask)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR((c_cpsr & ~0x2F) | mask);
return c_cpsr;
}
#pragma inline
static UNS_32 enable_irq_fiq_mask(UNS_32 mask)
{
UNS_32 c_cpsr;
c_cpsr = __get_CPSR();
__set_CPSR((c_cpsr & ~0x2F) & mask);
return c_cpsr;
}
#pragma inline
static UNS_32 restore_exceptions(UNS_32 old)
{
/* Not implemented yet */
return 0;
}
#endif /* __ICCARM__ */
#endif /* ABL_IRQ_FIQ_H */
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