lh79524_int_vec_gnu.asm

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

########################################################################
#  $Workfile:   lh79524_int_vec_gnu.asm  $
#  $Revision:   1.0  $
#  $Author:   ZhangJ  $
#  $Date:   Oct 20 2004 09:48:56  $
# 
#  Project: LH79524
# 
#  Description: 
#   This file contains code for exception handling and in particular,
#   IRQ handling. It is left to the application to install FIQ
#   handler code and manage FIQ interrupts.
#   The IRQ handler is split into three parts. The first part, the
#   "prologue", and the third part, the "epilogue", are mainly intended
#   for RTOSes. The prologue can be used to save status, registers that
#   may be modified and to re-enable interrupts so that nested 
#   interrupts can occur. The epilogue is meant for ISR post-processing,
#   like deciding to perform a context switch, or to just restore 
#   status and registers that were saved in the prologue.
#   The actual interrupt handler section is sandwiched between the 
#   prologue and epilogue. It loads the pc with the VIC vector address
#   register's address so that control is transferred directly to the
#   appropriate interrupt handler by the VIC. 
#   The ISRs can be written in C, and there is no need to use the __irq
#   keyword, because the prologue and epilogue ensure that context is
#   saved and restored. It is recommended that the prologue and epilogue
#   be written in assembly, at least until the bare minimum context is
#   saved/restored# the remaining part of the prologue/epilogue can be
#   written in C.
#
/*
#  Revision History:
#  $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh79524/source/lh79524_int_vec_gnu.asm-arc  $
; 
;    Rev 1.0   Oct 20 2004 09:48:56   ZhangJ
; Initial revision.
; 
;    Rev 1.2   Jul 08 2003 09:16:32   LiJ
; try again - revision added by PVCS can not compile
; 
;    Rev 1.1   Jul 08 2003 09:14:08   LiJ
; solve - revision added by PVCS can not compile
; 
;    Rev 1.0   Jul 07 2003 16:40:00   LiJ
; Initial revision.


*/
# 
# 
#  
########################################################################
#  
#   Copyright (c) 2002 Sharp Microelectronics of the Americas
# 
#   All rights reserved
# 
#   SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
#   OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
#   AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
#   SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
# 
#   SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
#   FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
#   SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
#   FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
# 
########################################################################

    .global  LH79524_irq_handler
    .global  LH79524_fiq_handler
    .global  LH79524_swi_handler
    .global  LH79524_irq_vec
    .global  LH79524_fiq_vec
    .global  LH79524_swi_vec    
    
    .extern  LH79524_fiq_handler_addr
    .extern  LH79524_swi_handler_addr
    .equ     LH79524_VIC_VECT_ADDR, 0xfffff030

    .text 
    .code 32
    .align 0
    
#-------------------------------------------------------------------
#
#
# Function: irq_vec
#
# Purpose:
#  Transfers control to LH79524_irq_handler() after an IRQ
#  exception.
# 
# Processing:
#  Load the address of LH79524_irq_dispatcher() stored at reserved
#  address 0x14 into the pc register.
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#---------------------------------------------------------------------

LH79524_irq_vec:
    # pc is 0x18 + 8. subtracting 12 yield 0x14.
    LDR     pc,[pc,#-12] 

#-------------------------------------------------------------------
#
#
# Function: LH79524_fiq_vec
#
# Purpose:
#  Transfers control to LH79524_fiq_handler() after an FIQ
#  exception.
# 
# Processing:
#  Load the address of LH79524_fiq_handler stored at reserved
#  address 0x24 into the pc register.
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#
#---------------------------------------------------------------------

LH79524_fiq_vec:
    # pc is 0x1C + 8. subtracting 0 yield 0x24.
    LDR     pc,[pc,#0x0] 

#-------------------------------------------------------------------
#
#
# Function: LH79524_swi_vec
#
# Purpose:
#  Transfers control to LH79524_swi_handler() after an SWI
#  exception.
# 
# Processing:
#  Load the address of LH79524_swi_handler() stored at reserved
#  address 0x20 into the pc register.
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#---------------------------------------------------------------------

LH79524_swi_vec:
    # pc is 0x8 + 8. adding 0x10 yield 0x20.
    LDR     pc,[pc,#0x10] 

    
#-------------------------------------------------------------------
#
#
# Function: LH79524_irq_handler
#
# Purpose: Handle IRQ exceptions
# 
# Processing:
# 1. Branch and link to the IRQ prologue 
# 2. Load the VIC vector address into PC
# 3. Write to the VIC vector address register to signal end 
#    of interrupt
# 4. Branch to epilogue
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#
#---------------------------------------------------------------------
LH79524_irq_handler:    

    # save link register
    SUB     lr,lr,#4
    # push registers    
    STMFD   sp!,{r0-r12,lr}
    MRS     v1, SPSR 
    STMFD   sp!,{v1}
    
    # save the link register for return after the ISR has executed
LH79524_vic_jump:   
    LDR     r0,=LH79524_VIC_VECT_ADDR
    MOV     lr,pc
    LDR     pc,[r0],#0

    # control returns here after the ISR has executed
    # write to the VIC Vector Address register to signal end-of-interrupt
    # to the VIC
    LDR     r0,=LH79524_VIC_VECT_ADDR
    MOV     r1,#0
    STR     r1,[r0,#0] 

    # branch to epilogue code    
    B   LH79524_default_irq_epilogue

#-------------------------------------------------------------------
#
#
# Function: LH79524_fiq_handler
#
# Purpose: Handle IRQ exceptions
# 
# Processing:
# 1. Load the handler vector address into PC
# 2. Branch to epilogue
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#
#---------------------------------------------------------------------
LH79524_fiq_handler:    

    # save link register
    SUB     lr,lr,#4
    # push registers    
    STMFD   sp!,{r0-r12,lr}
    MRS     v1, SPSR 
    STMFD   sp!,{v1}
    
    # save the link register for return after the ISR has executed
    LDR     r0,= LH79524_fiq_handler_addr
    MOV     lr,pc
    LDR     pc,[r0],#0

    # branch to epilogue code    
    B   LH79524_default_irq_epilogue

#-------------------------------------------------------------------
#
#
# Function: LH79524_swi_handler
#
# Purpose: Handle SWI exceptions
# 
# Processing:
# 1. Load the handler vector address into PC
# 2. Branch to epilogue
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#
#
#---------------------------------------------------------------------
LH79524_swi_handler:    

    # save link register
    SUB     lr,lr,#4
    # push registers    
    STMFD   sp!,{r0-r12,lr}
    MRS     v1, SPSR 
    STMFD   sp!,{v1}
    
    # save the link register for return after the ISR has executed
    LDR     r0,= LH79524_swi_handler_addr
    MOV     lr,pc
    LDR     pc,[r0],#0

    # control returns here after the ISR has executed
    # write to the VIC Vector Address register to signal end-of-interrupt
    # to the VIC
    LDR     r0,=LH79524_VIC_VECT_ADDR
    MOV     r1,#0
    STR     r1,[r0,#0] 

    # branch to epilogue code    
    B   LH79524_default_irq_epilogue


#-------------------------------------------------------------------
#
#
# Function: LH79524_default_irq_epilogue
#
# Purpose:
#   Perform post-processing after returning from an interrupt handler.
#   Meant to ease RTOS porting.
#
# Processing:
#   Restore registers and SPSR and switch out of IRQ mode
#
# Parameters: None
#
# Outputs:  None
#
# Returns: Nothing
#
# Notes:
#   This is primarily a placeholder for more extensive epilogue code
#   typical of any RTOS. This does very minimal post-processing. RTOSes
#   must not rely on this and replace this code with something that 
#   satisfys their specific requirements.
#
#
#---------------------------------------------------------------------
LH79524_default_irq_epilogue:   
    LDMFD   sp!,{v1}    
    MSREQ   SPSR_c,v1   
    #LDMFD   sp!,{r0-r12,pc}^
    LDMFD   sp!,{r0-r12}
    LDMFD   sp!,{pc}^
    .end