lh79524_rcpc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/**********************************************************************
 *  $Workfile:   lh79524_rcpc.h  $
 *  $Revision:   1.0  $
 *  $Author:   ZhangJ  $
 *  $Date:   Oct 20 2004 10:38:14  $
 *
 *  Project: LH79524 RCPC controller header file
 *
 *  Description:
 *      This file contains the definitions for RCPC controller on
 *      LH79524
 * 
 * Revision History:
 * $Log::   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps$
 * 
 *    Rev 1.0   Oct 20 2004 10:38:14   ZhangJ
 * Initial revision.
 * 
 *    Rev 1.2   Jul 20 2004 16:50:14   PattamattaD
 * Updated comments.
 * 
 *    Rev 1.1   Jun 25 2004 14:25:20   PattamattaD
 * Modified prescaler macros.
 * 
 *    Rev 1.0   Jun 15 2004 14:00:24   PattamattaD
 * Initial revision.
 * 
 * 
 *********************************************************************** 
 * 
 *  Copyright (c) 2004 Sharp Microelectronics of the Americas 
 * 
 *  All rights reserved 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
 * 
 **********************************************************************/

#ifndef LH79524_RCPC_H
#define LH79524_RCPC_H

#include "lh79524_chip.h"

/**********************************************************************
 * Reset, Clock, and Power Controller Register Structure
 *********************************************************************/ 
typedef struct 
{
  volatile UNS_32 rcpcctrl;        /* RCPC Control */ 
  volatile UNS_32 identification;  /* ID Register */ 
  volatile UNS_32 remap;           /* Remap Control */ 
  volatile UNS_32 softreset;       /* Soft Reset */ 
  volatile UNS_32 resetstatus;     /* Reset Status */ 
  volatile UNS_32 resetstatusclr;  /* Reset Status Clear */ 
  volatile UNS_32 hclkprescale;    /* HCLK Prescale */ 
  volatile UNS_32 cpuclkprescale;  /* Core Clock Prescale */ 
  volatile UNS_32 reserved1;        
  volatile UNS_32 periphclkctrl0;  /* Peripheral Clock Ctrl 0*/ 
  volatile UNS_32 periphclkctrl1;  /* Peripheral Clock Ctrl 1*/
  volatile UNS_32 ahbclkctrl;      /* AHB Clock Ctrl */ 
  volatile UNS_32 reserved2;    
  volatile UNS_32 periphclksel;    /* Peripheral Clock Select*/
  volatile UNS_32 reserved3[2];    
  volatile UNS_32 lcdclkprescale;  /* LCD clock Prescale */
  volatile UNS_32 sspclkprescale;  /* SSP clock Prescale */
  volatile UNS_32 adcclkprescale;  /* ADC clock Prescale */
  volatile UNS_32 usbclkprescale;  /* USB clock Prescale */
  volatile UNS_32 reserved4[12];   
  volatile UNS_32 intconfig;       /* Ext. Interrupt Config */
  volatile UNS_32 intclear;        /* Ext. Interrupt Clear  */
  volatile UNS_32 coreclkconfig;   /* Core Clock Config */
  volatile UNS_32 reserved5[13];   
  volatile UNS_32 systempllctrl;   /* System PLL Control Register */
  volatile UNS_32 usbpllctrl;   /* USB PLL Control Register */
} RCPC_REGS_T;

/**********************************************************************
 * Reset, Clock, and Power Controller Register Bit Fields
 *********************************************************************/ 

/**********************************************************************
 * rcpcctrl - RCPCCtrl Register Bit Fields
 *********************************************************************/ 
/* bit fields for power down mode */
#define RCPC_CTRL_PWRDWNSEL(n)  _SBF(2,(n)) /* Power Down Mode Sel*/ 
/* bit fields for power down mode - active mode*/
#define RCPC_PWRDWNSEL_ACTIVE    RCPC_CTRL_PWRDWNSEL(0)
/* bit fields for power down mode - standby mode*/
#define RCPC_PWRDWNSEL_STANDBY   RCPC_CTRL_PWRDWNSEL(1)
/* bit fields for power down mode - sleep mode */
#define RCPC_PWRDWNSEL_SLEEP     RCPC_CTRL_PWRDWNSEL(2)
/* bit fields for power down mode - stop1 mode */
#define RCPC_PWRDWNSEL_STOP1     RCPC_CTRL_PWRDWNSEL(3)
/* bit fields for power down mode - stop2 mode */
#define RCPC_PWRDWNSEL_STOP2     RCPC_CTRL_PWRDWNSEL(4)

/* bit fields for output selection field */
#define RCPC_CTRL_OUTSEL(n)     _SBF(5,(n))
/* bit fields for clock output selection - System Clock Oscillator Clock */
#define RCPC_OUTSEL_CLK_SYSOSC   RCPC_CTRL_OUTSEL(0)
/* bit fields for clock output selection field - clock use fclk */
#define RCPC_OUTSEL_FCLK_CPU     RCPC_CTRL_OUTSEL(2)
/* bit fields for clock output selection field - clock use hclk */
#define RCPC_OUTSEL_HCLK         RCPC_CTRL_OUTSEL(3)

/* bit fields for RCPC controller write lock bit - locked */
#define RCPC_CTRL_WRTLOCK_LOCKED    _SBF(9,0)
/* bit fields for RCPC controller write lock bit - unlocked */
#define RCPC_CTRL_WRTLOCK_UNLOCKED   _SBF(9,1)

/**********************************************************************
 * remap - Remap Control Register Bit Fields
 *********************************************************************/ 
/* bit fields for remap register - set nCS1 static memory at address 0x0 */
#define RCPC_REMAP_CS1MEM0    (0)
/* bit fields for remap register - set nDCS0 SDRAM at address 0x0 */
#define RCPC_REMAP_DCS0MEM0   (1)
/* bit fields for remap register - set internal SRAM at address 0x0 */
#define RCPC_REMAP_IMEM0      (2)
/* bit fields for remap register - set nCS0 static memory at address 0x0 */
#define RCPC_REMAP_CS0MEM0    (3)

/**********************************************************************
 * softreset - Soft Reset Register Bit Fields
 *********************************************************************/ 
/* bit fields for software reset register - reset all */
#define RCPC_SOFTRESET_ALL  (0xDEAD)

/**********************************************************************
 * resetstatus, resetstatusclr - Reset Status Register Bit Fields
 *********************************************************************/ 
/* bit fields for reset status register - reset from external */
#define RCPC_RESET_STATUS_EXT   _BIT(0)
/* bit fields for reset status register - reset from watch dog timer */
#define RCPC_RESET_STATUS_WDTO  _BIT(1)

/**********************************************************************
 * hclkPrescale - HCLK Prescaler Register Bit Fields
 * cpuclkPrescale - Core Clock Prescaler Register Bit Fields
 * sparePrescale - Spare Prescaler Register Bit Fields
 * Note: not all constants are applicable to all registers.
 *  See Reference.
 *********************************************************************/ 
/* bit fields for prescaler divider value - divider is 1 */
#define RCPC_PRESCALER_DIV1     _SBF(0,0)
/* bit fields for prescaler divider value - divider is 2 */
#define RCPC_PRESCALER_DIV2     _SBF(0,1)
/* bit fields for prescaler divider value - divider is 4 */
#define RCPC_PRESCALER_DIV4     _SBF(0,2)
/* bit fields for prescaler divider value - divider is 6 */
#define RCPC_PRESCALER_DIV6     _SBF(0,3)
/* bit fields for prescaler divider value - divider is 8 */
#define RCPC_PRESCALER_DIV8     _SBF(0,4)
/* bit fields for prescaler divider value - divider is 16 */
#define RCPC_PRESCALER_DIV16    _SBF(0,8)
/* bit fields for prescaler divider value - divider is 30 */