lh79524_emc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/***********************************************************************
 * $Workfile:   lh79524_emc.h  $
 * $Revision:   1.0  $
 * $Author:   ZhangJ  $
 * $Date:   Oct 20 2004 10:38:12  $
 *
 * Project: LH79524 headers
 *
 * Description: 
 *      This file contains the structure definitions and manifest
 *      constants for LH79524 component:
 *
 *          External Memory Controller
 *
 * Revision History:
 * $Log::   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps$
 * 
 *    Rev 1.0   Oct 20 2004 10:38:12   ZhangJ
 * Initial revision.
 * 
 *    Rev 1.2   Jul 20 2004 16:50:14   PattamattaD
 * Updated comments.
 * 
 *    Rev 1.1   Jun 25 2004 14:23:14   PattamattaD
 * Addded read config register.
 * 
 *    Rev 1.0   Jun 15 2004 14:00:16   PattamattaD
 * Initial revision.
 * 
 * 
 ***********************************************************************
 * 
 *  Copyright (c) 2004 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 **********************************************************************/
#ifndef LH79524_EMC_H
#define LH79524_EMC_H

#include "abl_types.h"
#include "lh79524_chip.h"

/***********************************************************************
 * External Memory Controller Module Register Structure
 **********************************************************************/

typedef struct
{
  /* Control Register */
  volatile UNS_32 ctrl;     
  /* Status Register */
  volatile UNS_32 status;
  /* Configuration Register */
  volatile UNS_32 config;
  UNS_32   reserved0[5];
  /* Dynamic Memory Control Register */
  volatile UNS_32 sdramc_ctrl;
  /* Dynamic Memory Refresh Timer */
  volatile UNS_32 sdramc_refresh;
  /* Dynamic Memory read configuration Register */
  volatile UNS_32 sdramc_read_config;
  UNS_32   reserved1;
  /* Dynamic Memory Precharge Command Period */
  volatile UNS_32 sdramc_rp;
  /* Dynamic Memory Active to Precharge Command Period */
  volatile UNS_32 sdramc_ras;
  /* Dynamic Memory Self-Refresh Exit Time */
  volatile UNS_32 sdramc_srex;
  /* Dynamic Memory Last Data Out to Active Time */
  volatile UNS_32 sdramc_apr;
  /* Dynamic Memory Data-In to Active Command Time */
  volatile UNS_32 sdramc_dal;
  /* Dynamic Memory Write Recovery Time */
  volatile UNS_32 sdramc_wr;
  /* Dynamic Memory Active to Active Command Period */
  volatile UNS_32 sdramc_rc;
  /* Dynamic Memory Auto-Refresh Period, and Auto-Refresh
     to Active Command Period */
  volatile UNS_32 sdramc_rfc;
  /* Dynamic Memory Exit Self-Refresh to Active Command Time */
  volatile UNS_32 sdramc_xsr;
  /* Dynamic Memory Active Bank A to Active Bank B Time */
  volatile UNS_32 sdramc_rrd;
  /* Dynamic Memory Load Mode Register to Active Command Time */
  volatile UNS_32 sdramc_mrd;
  UNS_32   reserved2[9];
  /* Static Memory Extended Wait */
  volatile UNS_32 static_ext_wait;
  UNS_32   reserved3[31];
  /* Dynamic Configuration Register for nDCS0 */
  volatile UNS_32 sdramc_cfg0;
  /* Dynamic Memory RAS and CAS Delay for nDCS0 */
  volatile UNS_32 sdramc_rascas0;
  UNS_32   reserved4[6];
  /* Dynamic Configuration Register for nDCS1 */
  volatile UNS_32 sdramc_cfg1;
  /* Dynamic Memory RAS and CAS Delay for nDCS1 */
  volatile UNS_32 sdramc_rascas1;
  UNS_32   reserved5[54];
  /* Static Memory Configuration for nCS0 */
  volatile UNS_32 static_cfg0;
  /* Static Memory Write Enable Delay for nCS0 */
  volatile UNS_32 static_waitwen0;
  /* Static Memory Output Enable Delay for nCS0 */
  volatile UNS_32 static_waitoen0;
  /* Static Memory Read Delay for nCS0 */
  volatile UNS_32 static_waitrd0;
  /* Static Memory Page Mode Read Delay for nCS0 */
  volatile UNS_32 static_waitpage0;
  /* Static Memory Write Delay for nCS0 */
  volatile UNS_32 static_waitwr0;
  /* Static Memory Turn Around Delay for nCS0 */
  volatile UNS_32 static_waitturn0;
  UNS_32 reserved6;
  /* Static Memory Configuration for nCS1 */
  volatile UNS_32 static_cfg1;
  /* Static Memory Write Enable Delay for nCS1 */
  volatile UNS_32 static_waitwen1;
  /* Static Memory Output Enable Delay for nCS1 */
  volatile UNS_32 static_waitoen1;
  /* Static Memory Read Delay for nCS1 */
  volatile UNS_32 static_waitrd1;
  /* Static Memory Page Mode Read Delay for nCS1 */
  volatile UNS_32 static_waitpage1;
  /* Static Memory Write Delay for nCS1 */
  volatile UNS_32 static_waitwr1;
  /* Static Memory Turn Around Delay for nCS1 */
  volatile UNS_32 static_waitturn1;
  UNS_32 reserved7;
  /* Static Memory Configuration for nCS2 */
  volatile UNS_32 static_cfg2;
  /* Static Memory Write Enable Delay for nCS2 */
  volatile UNS_32 static_waitwen2;
  /* Static Memory Output Enable Delay for nCS2 */
  volatile UNS_32 static_waitoen2;
  /* Static Memory Read Delay for nCS2 */
  volatile UNS_32 static_waitrd2;
  /* Static Memory Page Mode Read Delay for nCS2 */
  volatile UNS_32 static_waitpage2;
  /* Static Memory Write Delay for nCS2 */
  volatile UNS_32 static_waitwr2;
  /* Static Memory Turn Around Delay for nCS2 */
  volatile UNS_32 static_waitturn2;
  UNS_32 reserved8;
  /* Static Memory Configuration for nCS3 */
  volatile UNS_32 static_cfg3;
  /* Static Memory Write Enable Delay for nCS3 */
  volatile UNS_32 static_waitwen3;
  /* Static Memory Output Enable Delay for nCS3 */
  volatile UNS_32 static_waitoen3;
  /* Static Memory Read Delay for nCS3 */
  volatile UNS_32 static_waitrd3;
  /* Static Memory Page Mode Read Delay for nCS3 */
  volatile UNS_32 static_waitpage3;
  /* Static Memory Write Delay for nCS3 */
  volatile UNS_32 static_waitwr3;
  /* Static Memory Turn Around Delay for nCS3 */
  volatile UNS_32 static_waitturn3;
  UNS_32 reserved9;
} EMC_REGS_T;

/***********************************************************************
 * External Memory Controller Bit Field constants
 **********************************************************************/
 
#define EMC_CTL_ENABLE                _BIT(0)
#define EMC_CTL_LOW_PWR               _BIT(2)

#define EMC_STATUS_SA                 _BIT(2)
#define EMC_STATUS_WR_BUF             _BIT(1)
#define EMC_STATUS_BUSY               _BIT(0)

#define EMC_CFG_SDCCLK_1_2            _BIT(8)
#define EMC_CFG_SDCCLK_1_1            (0)

#define EMC_SDRAMC_CTL_CE             _BIT(0)