📄 lh79524_iocon.h
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/**********************************************************************
* $Workfile: lh79524_iocon.h $
* $Revision: 1.0 $
* $Author: ZhangJ $
* $Date: Oct 20 2004 10:38:14 $
*
* Project: LH79524 IOCON controller header file
*
* Description:
* This file contains the definitions for IOCON controller on
* LH79524
*
* Revision History:
* $Log:: //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csp$
*
* Rev 1.0 Oct 20 2004 10:38:14 ZhangJ
* Initial revision.
*
* Rev 1.2 Jul 20 2004 16:50:14 PattamattaD
* Updated comments.
*
* Rev 1.1 Jun 25 2004 14:24:00 PattamattaD
* Added bit position defines for MuxCtl25.
*
* Rev 1.0 Jun 15 2004 14:00:22 PattamattaD
* Initial revision.
*
*
*
***********************************************************************
*
* Copyright (c) 2004 Sharp Microelectronics of the Americas
*
* All rights reserved
*
* SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
* OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
* AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
* SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
*
* SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
* FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
* SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
* FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
*
**********************************************************************/
#ifndef LH79524_IOCON_H
#define LH79524_IOCON_H
#include "lh79524_chip.h"
/***********************************************************************
* IO Configuration Block Structure
**********************************************************************/
typedef struct
{
volatile UNS_32 mux_ctl_1;
volatile UNS_32 res_ctl_1;
volatile UNS_32 reserved0[2];
volatile UNS_32 mux_ctl_3;
volatile UNS_32 res_ctl_3;
volatile UNS_32 mux_ctl_4;
volatile UNS_32 res_ctl_4;
volatile UNS_32 mux_ctl_5;
volatile UNS_32 res_ctl_5;
volatile UNS_32 mux_ctl_6;
volatile UNS_32 res_ctl_6;
volatile UNS_32 mux_ctl_7;
volatile UNS_32 res_ctl_7;
volatile UNS_32 reserved1[4];
volatile UNS_32 mux_ctl_10;
volatile UNS_32 res_ctl_10;
volatile UNS_32 mux_ctl_11;
volatile UNS_32 res_ctl_11;
volatile UNS_32 mux_ctl_12;
volatile UNS_32 res_ctl_12;
volatile UNS_32 reserved2;
volatile UNS_32 res_ctl_13;
volatile UNS_32 mux_ctl_14;
volatile UNS_32 reserved3;
volatile UNS_32 mux_ctl_15;
volatile UNS_32 res_ctl_15;
volatile UNS_32 reserved4[3];
volatile UNS_32 res_ctl_17;
volatile UNS_32 reserved5[2];
volatile UNS_32 mux_ctl_19;
volatile UNS_32 res_ctl_19;
volatile UNS_32 mux_ctl_20;
volatile UNS_32 res_ctl_20;
volatile UNS_32 mux_ctl_21;
volatile UNS_32 res_ctl_21;
volatile UNS_32 mux_ctl_22;
volatile UNS_32 res_ctl_22;
volatile UNS_32 mux_ctl_23;
volatile UNS_32 res_ctl_23;
volatile UNS_32 mux_ctl_24;
volatile UNS_32 res_ctl_24;
volatile UNS_32 mux_ctl_25;
} IOCON_REGS_T;
/***********************************************************************
* Resistor Multiplexing IOCON Register Bit Field macros
*
**********************************************************************/
#define IOCON_PULLDOWN_VAL 1
#define IOCON_PULLUP_VAL 2
#define IOCON_FLOAT_VAL 0
#define IOCON_RES_MASK _BITMASK(2)
#define IOCON_RES_SET(n,val) _SBF(((n) * 2), val)
#define IOCON_PULLDOWN(n) IOCON_RES_SET(n,IOCON_PULLDOWN_VAL)
#define IOCON_PULLUP(n) IOCON_RES_SET(n,IOCON_PULLUP_VAL)
#define IOCON_FLOAT(n) IOCON_RES_SET(n,IOCON_FLOAT_VAL)
#define IOCON_MUX_MASK(n) ~(_SBF(n,_BITMASK(2)))
#define IOCON_RES1_PI2_ETHERCOL 8
#define IOCON_RES1_PI1_ETHERMDIO 6
#define IOCON_RES1_PI0_ETHERMDC 4
#define IOCON_RES1_PL1_LCDVD15 2
#define IOCON_RES1_PL0_LCDVD14 0
#define IOCON_RES3_CTCLK_INT4_BATCNTL 0
#define IOCON_RES4_PA7_CTCAP2B_CTCMP2B_SCL 10
#define IOCON_RES4_PA6_CTCAP2A_CTCMP2A_SDA 8
#define IOCON_RES4_PA5_CTCAP1B_CTCMP1B 6
#define IOCON_RES4_PA7_PA4_CTCAP1A_CTCMP1A 4
#define IOCON_RES4_PA3_CTCAP0B_CTCMP0B 2
#define IOCON_RES4_PA2_CTCAP0A_CTCMP0A 0
#define IOCON_RES5_PA1_INT3_UARTTX2_UARTIRTX2 14
#define IOCON_RES5_PA0_INT2_UARTRX2_UARTIRRX2 12
#define IOCON_RES5_PB7_INT1_UARTTX0_UARTIRTX0 10
#define IOCON_RES5_PB6_INT0_UARTRX0_UARTIRRX0 8
#define IOCON_RES5_PB5_SSPTX_I2STXD_UARTTX1_UARTIRTX1 6
#define IOCON_RES5_PB4_SSPRX_I2STXD_UARTRX1_UARTIRRX1 4
#define IOCON_RES5_PB3_SSPCLK_I2SLCK 2
#define IOCON_RES5_PB2_SSPFRM_I2SWS 0
#define IOCON_RES6_PB1_DREQ_UARTRTS0 2
#define IOCON_RES6_PB0_DACK_UARTCTS0 0
#define IOCON_RES7_PC7_A23_nFRE 14
#define IOCON_RES7_PC6_A22_nFWE 12
#define IOCON_RES7_PC5_A21 10
#define IOCON_RES7_PC4_A20 8
#define IOCON_RES7_PC3_A19 6
#define IOCON_RES7_PC2_A18 4
#define IOCON_RES7_PC1_A17 2
#define IOCON_RES7_PC0_A16 0
#define IOCON_RES10_PN3_D25 14
#define IOCON_RES10_PN2_D24 12
#define IOCON_RES10_PD7_D15 10
#define IOCON_RES10_PK7_D23 8
#define IOCON_RES10_PD6_D14 6
#define IOCON_RES10_PK6_D22 4
#define IOCON_RES10_PD5_D13 2
#define IOCON_RES10_PK5_D21 0
#define IOCON_RES11_PD4_D12 14
#define IOCON_RES11_PK4_D20 12
#define IOCON_RES11_PD3_D11 10
#define IOCON_RES11_PK3_D19 8
#define IOCON_RES11_PD2_D10 6
#define IOCON_RES11_PK2_D18 4
#define IOCON_RES11_PK1_D17 2
#define IOCON_RES11_PD1_D9 0
#define IOCON_RES12_PK0_D16 14
#define IOCON_RES12_PD0_D8 12
#define IOCON_RES12_D7 10
#define IOCON_RES12_D6 8
#define IOCON_RES12_D5 6
#define IOCON_RES12_D4 4
#define IOCON_RES12_D3 2
#define IOCON_RES12_D2 0
#define IOCON_RES13_D1 2
#define IOCON_RES13_D0 0
#define IOCON_RES15_BLE0_PM4 0
#define IOCON_RES17_SDCLK 0
#define IOCON_RES19_PE7_WAIT_DEOT 14
#define IOCON_RES19_PE6_LCDVEEN_LCDMOD 12
#define IOCON_RES19_PL7_D31 10
#define IOCON_RES19_PE5_LCDVDDEN 8
#define IOCON_RES19_PL6_D30 6
#define IOCON_RES19_PE4_LCDSPLEN_LCDREV 4
#define IOCON_RES19_PE3_LCDCLS 2
#define IOCON_RES19_PL5_D29 0
#define IOCON_RES20_PE2_LCDPS 14
#define IOCON_RES20_PL4_D28 12
#define IOCON_RES20_PE1_LCDDCLK 10
#define IOCON_RES20_PN1_D27 8
#define IOCON_RES20_PE0_LCDLP_LCDHRLP 6
#define IOCON_RES20_PN0_D26 4
#define IOCON_RES20_PF7_LCDFP_LCDSPS 2
#define IOCON_RES20_PF6_LCDEN_LCDSPL 0
#define IOCON_RES21_PF5_LCDVD11 10
#define IOCON_RES21_PL3_LCDVD13 8
#define IOCON_RES21_PF4_LCDVD10 6
#define IOCON_RES21_PL2_LCDVD12 4
#define IOCON_RES21_PF3_LCDVD9 2
#define IOCON_RES21_PF2_LCDVD8 0
#define IOCON_RES22_PF1_LCDVD7 14
#define IOCON_RES22_PF0_LCDVD6 12
#define IOCON_RES22_PG7_LCDVD5 10
#define IOCON_RES22_PG6_LCDVD4 8
#define IOCON_RES22_PG5_LCDVD3 6
#define IOCON_RES22_PG4_LCDVD2 4
#define IOCON_RES22_PG3_LCDVD1 2
#define IOCON_RES22_PG2_LCDVD0 0
#define IOCON_RES23_PG1_ETHERTXCLK 14
#define IOCON_RES23_PG0_ETHERTXEN 12
#define IOCON_RES23_PH7_ETHERTX3 10
#define IOCON_RES23_PH6_ETHERTX2 8
#define IOCON_RES23_PH5_ETHERTX1 6
#define IOCON_RES23_PH4_ETHERTX0 4
#define IOCON_RES23_PH3_ETHERTXER 2
#define IOCON_RES23_PH2_ETHERRXCLK 0
#define IOCON_RES24_PH1_ETHERRXDV 12
#define IOCON_RES24_PH0_ETHERRX3 10
#define IOCON_RES24_PI7_ETHERRX2 8
#define IOCON_RES24_PI6_ETHERRX1 6
#define IOCON_RES24_PI5_ETHERRX0 4
#define IOCON_RES24_PI4_ETHERRXER 2
#define IOCON_RES24_PI3_ETHERCRS 0
#define IOCON_RES25_AN6_PJ7_INT7 14
#define IOCON_RES25_AN7_PJ6_INT6 12
#define IOCON_RES25_AN5_PJ5_INT5 10
#define IOCON_RES25_AN8_PJ4 8
#define IOCON_RES25_AN2_PJ3 6
#define IOCON_RES25_AN9_PJ2 4
#define IOCON_RES25_AN4_PJ1 2
#define IOCON_RES25_AN3_PJ0 0
/***********************************************************************
#define IOCON_RES * IOCON Multiplexing Register Bit Field macros
*
**********************************************************************/
#define IOCON_MUX1_ETHERCOL _SBF(8,1)
#define IOCON_MUX1_PI2 _SBF(8,0)
#define IOCON_MUX1_ETHERMDIO _SBF(6,1)
#define IOCON_MUX1_PI1 _SBF(6,0)
#define IOCON_MUX1_ETHERMDC _SBF(4,1)
#define IOCON_MUX1_PI0 _SBF(4,0)
#define IOCON_MUX1_LCDVD15 _SBF(2,1)
#define IOCON_MUX1_PL1 _SBF(2,0)
#define IOCON_MUX1_LCDVD14 _SBF(0,1)
#define IOCON_MUX1_PL0 _SBF(0,0)
#define IOCON_MUX3_CTCLK _SBF(0,0)
#define IOCON_MUX3_INT4 _SBF(0,1)
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