lh79524_adc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

 * ADC results register defines
 **********************************************************************/
/* ADC control bank tag mask */
#define ADC_CBANKTAG       _BITMASK(4)  
/* Macro for shifting and reading the ADC converter output value */
#define ADC_READ_OUTPUT(n) (((n) >> 6) & _BITMASK(10))

/***********************************************************************
 * ADC interrupt enable register defines
 **********************************************************************/
/* ADC FIFO overrun enable and status bit */
#define ADC_FIFO_OV_INT    _BIT(0)  
/* ADC watermark enable and status bit */                                         
#define ADC_WATERM_INT     _BIT(1)  
/* ADC end of sequence enable  and status bit */                                      
#define ADC_EOS_INT        _BIT(2)  
/* ADC pen interrupt enable and status bit */                                     
#define ADC_PEN_INT        _BIT(3)  
/* ADC brownout interrupt enable bit (IRQ) */                                        
#define ADC_BROWN_IRQ_INT  _BIT(4)  
/* ADC brownout  interrupt independent of the combined TSCINTR 
   interrupt enable bit*/                                         
#define ADC_BROWN_ISE_INT  _BIT(5)  
/* ADC global interrupt enable bit */                                 
#define ADC_GLOBAL_INT     _BIT(6)  
                                          

/***********************************************************************
 * ADC power configuation register defines
 **********************************************************************/

/* ADC number of conversions in sequence load mask */
#define ADC_NOC_SET(n)     (((n) - 1) & _BITMASK(4))
/* ADC number of conversions bit mask */
#define ADC_NOC_MASK       _BITMASK(4) 
/* ADC Battery Control enable bit */
#define ADC_BAT_ENABLE     _BIT(4)    
/* ADC internal reference buffer enable bit */                                       
#define ADC_REF_ENABLE     _BIT(5)     
/* ADC power mode bitfield mask */                                       
#define ADC_PWM_MASK       _SBF(6,_BITMASK(2))
/* ADC power mode and clock off */                                      
#define ADC_PWM_ALL_OFF    _SBF(6,0x0)  
/* ADC standby mode */                                         
#define ADC_PWM_STANDBY    _SBF(6,0x1)
/* ADC run (always on) mode */  
#define ADC_PWM_RUN        _SBF(6,0x2)  
/* ADC clock selection bitfield mask */
#define ADC_CLKSEL_MASK    _SBF(8,_BITMASK(3))  
/* ADC clock selection bitfield width */
#define ADC_CLKSEL_WIDTH   3  
                                         
#define ADC_CLKSEL_DIV1    _SBF(8,0x0) /* ADC clock is divide by 1 */
#define ADC_CLKSEL_DIV2    _SBF(8,0x1) /* ADC clock is divide by 2 */
#define ADC_CLKSEL_DIV4    _SBF(8,0x2) /* ADC clock is divide by 4 */
#define ADC_CLKSEL_DIV8    _SBF(8,0x3) /* ADC clock is divide by 8 */
#define ADC_CLKSEL_DIV16   _SBF(8,0x4) /* ADC clock is divide by 16 */
#define ADC_CLKSEL_DIV32   _SBF(8,0x5) /* ADC clock is divide by 32 */
#define ADC_CLKSEL_DIV64   _SBF(8,0x6) /* ADC clock is divide by 64 */
#define ADC_CLKSEL_DIV128  _SBF(8,0x7) /* ADC clock is divide by 128 */
/* ADC clock divider load macro, clock divider = 2^n */
#define ADC_CLKSEL_SET(n)  (((n) & 0x7) << 8)
#define ADC_CLKSEL_GET(n)   (((n) & ADC_CLKSEL_MASK) >> 8)

/***********************************************************************
 * Physical limits on the ADC clock (Hz)
 **********************************************************************/
#define ADC_MAX_CLK 2000000
#define ADC_MIN_CLK 200000

/***********************************************************************
 * ADC general configuration register defines
 **********************************************************************/
/* ADC sequence start mode mask */
#define ADC_SSM_MASK       _BITMASK(2)  
/* ADC SSB or pen interrupt starts new conversions */                                        
#define ADC_SSM_SSB_PEN    _SBF(0,0x0)  
/* ADC Pen interrupt starts new conversions */                                         
#define ADC_SSM_PEN        _SBF(0,0x1)  
/* ADC SSB starts new conversions */                                         
#define ADC_SSM_SSB        _SBF(0,0x2)
/* ADC Continuous conversions */  
#define ADC_SSM_CONT       _SBF(0,0x3)
/* ADC SSB conversion sequence start enable bit */ 
#define ADC_SSB_START      _BIT(2)  
/* ADC watermark mask */                                         
#define ADC_WM_MASK        _SBF(3,_BITMASK(4))  
/* ADC load macro to set the watermark level for the conversion FIFO */
#define ADC_WM_SET(n)      ((((n) - 1) & 0xF) << 3)

/***********************************************************************
 * ADC general status register defines
 **********************************************************************/
/* ADC current conversion number tag mask */
#define ADC_CBTAG_MASK     _BITMASK(4) 
/* ADC control bank state machine status mask */                                         
#define ADC_SM_MASK        _SBF(4,_BITMASK(4))  
/* ADC state machine idle */                                         
#define ADC_SM_IDLE        _SBF(4,0x00)
/* ADC state machine is getting data */ 
#define ADC_SM_GETDATA     _SBF(4,0x02)  
/* ADC state machine is waiting for conversion */                                        
#define ADC_SM_WAITCONV    _SBF(4,0x04)  
/* ADC state machine at end of sequence */                                        
#define ADC_SM_EOS         _SBF(4,0x08)  
/* ADC pen raw interrupt status bit */                                         
#define ADC_PENINT         _BIT(8)  
/* ADC brownout raw interrupt status bit */                                         
#define ADC_BROWNOUTINT    _BIT(9)  
                                         

/***********************************************************************
 * ADC raw and masked interrupt status register defines
 **********************************************************************/

#define ADC_FIFO_OV_IRQ    _BIT(0)  /* ADC FIFO overrun raw interrupt
                                          is active */
#define ADC_WATERM_IRQ     _BIT(1)  /* ADC FIFO watermark raw
                                          interrupt is active */
#define ADC_EOS_IRQ        _BIT(2)  /* ADC FIFO endo of sequence raw
                                          interrupt is active */
#define ADC_PEN_IRQ        _BIT(3)  /* ADC FIFO pen raw interrupt is
                                          active */
#define ADC_BROWNOUT_IRQ   _BIT(4)  /* ADC FIFO brownout raw
                                          interrupt is active */

/***********************************************************************
 * ADC FIFO status register defines
 **********************************************************************/

#define ADC_FIFO_GTEWM     _BIT(0)  /* ADC FIFO is at or above
                                          watermark level */
#define AFC_FIFO_OV        _BIT(1)  /* ADC FIFO has overrun */
#define ADC_FIFO_EMPTY     _BIT(2)  /* ADC FIFO is empty */
#define ADC_FIFO_FULL      _BIT(3)  /* ADC FIFO is full */
/* ADC FIFO read pointer load macro */
#define ADC_FIFO_RDPTR(n)  _SBF(4,((n) & _BITMASK(4)))
/* ADC FIFO write pointer load macro */
#define ADC_FIFO_WRPTR(n)  _SBF(8,((n) & _BITMASK(4)))

/***********************************************************************
 * ADC interrupt clear register defines
 **********************************************************************/

#define ADC_EOS_CLR        _BIT(0) /* ADC EOS interrupt clear bit */
#define ADC_PEN_CLR        _BIT(1) /* ADC pen interrupt clear bit */
#define ADC_BROWNOUT_CLR   _BIT(2) /* ADC brownout interrupt clear
                                         bit */

/***********************************************************************
 * ADC miscellaneous defines
 **********************************************************************/

/* Number of ADC clocks needed to perform a conversion */
#define ADC_SAMPLE_CLKS    17

/* Macro pointing to ADC registers */
#define ADC ((ADC_REGS_T *)(ADC_BASE))

#endif /*LH79524_ADC_H */