lh79524_adc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/***********************************************************************
 * $Workfile:   lh79524_adc.h  $
 * $Revision:   1.0  $
 * $Author:   ZhangJ  $
 * $Date:   Oct 20 2004 10:38:10  $
 *
 * Project: LH79524 ADC definitions
 *
 * Description:
 *     This file contains the structure definitions and manifest
 *     constants for LH79524 component:
 *         Analog to Digital Converter / Touchscreen Controller
 *
 * Revision History:
 * $Log::   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps$
 * 
 *    Rev 1.0   Oct 20 2004 10:38:10   ZhangJ
 * Initial revision.
 * 
 *    Rev 1.1   Jul 20 2004 16:50:08   PattamattaD
 * Updated comments.
 * 
 *    Rev 1.0   Jun 25 2004 14:21:06   PattamattaD
 * Initial revision.
 * 
 *
 *
 ***********************************************************************
 * 
 *  Copyright (c) 2004 Sharp Microelectronics of the Americas 
 * 
 *  All rights reserved 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
 * 
 **********************************************************************/

#ifndef LH79524_ADC_H
#define LH79524_ADC_H

#include "abl_types.h"
#include "lh79524_chip.h"

/***********************************************************************
 * ADC Module Register Structure
 **********************************************************************/

/* ADC Module Register Structure */ 
typedef struct 
{
  volatile UNS_32 adchiword;  /* ADC control bank high word
                                 register */
  volatile UNS_32 adcloword;  /* ADC control bank low word register */
  volatile UNS_32 adcresults; /* ADC results register */
  volatile UNS_32 adcie;      /* ADC interrupt enable register */
  volatile UNS_32 adcpcr;     /* ADC power configuation register */
  volatile UNS_32 adcgencfg;  /* ADC general configuration register */
  volatile UNS_32 adcgensts;  /* ADSC general status register */
  volatile UNS_32 adcrawint;  /* ADC raw interrupt status register */
  volatile UNS_32 adcfifosts; /* ADC FIFO status register */
  volatile UNS_32 adchicl[16]; /* ADC high control bank registers */
  volatile UNS_32 adclocl[16]; /* ADC low control bank registers */
  volatile UNS_32 adcidlehi;  /* ADC idle high word register */
  volatile UNS_32 adcidlelo;  /* ADC idle low word register */
  volatile UNS_32 adcmis;     /* ADC masked interrupt status
                                 register */
  volatile UNS_32 adcic;      /* ADC interrupt clear register */
} ADC_REGS_T;

/***********************************************************************
 * ADC control bank high word register defines
 * ADC IN+ MUX definitions used with ADC_INP_MASK
 **********************************************************************/

#define ADC_INP_AN0        _SBF(3,0x00)  /* ADC analog 0 input (UL/X+) */
#define ADC_INP_AN1        _SBF(3,0x01)  /* ADC analog 1 input (UR/X-) */
#define ADC_INP_AN2        _SBF(3,0x02)  /* ADC analog 2 input (LL/Y+) */
#define ADC_INP_AN3        _SBF(3,0x03)  /* ADC analog 3 input (LL/Y-) */
#define ADC_INP_AN4        _SBF(3,0x04)  /* ADC analog 4 input (WIPER) */
#define ADC_INP_AN5        _SBF(3,0x05)  /* ADC analog 5 (reserved) */
#define ADC_INP_AN6        _SBF(3,0x06)  /* ADC analog 6 input */
#define ADC_INP_AN7        _SBF(3,0x07)  /* ADC analog 7 (reserved) */
#define ADC_INP_AN8        _SBF(3,0x08)  /* ADC analog 8 input */
#define ADC_INP_AN9        _SBF(3,0x09)  /* ADC analog 9 input */
#define ADC_INP_AN10       _SBF(3,0x0A)  /* ADC analog 10 input (VREF-) */

/***********************************************************************
 * ADC control bank high word register defines
 * ADC REF+ MUX definitions used with ADC_REF_MASK
 **********************************************************************/

#define ADC_REF_VREFP      _SBF(0,0x00)  /* Reference is VREF+ */
#define ADC_REF_AN0        _SBF(0,0x01)  /* Reference is AN0 */
#define ADC_REF_AN2        _SBF(0,0x02)  /* Reference is AN2 */
#define ADC_REF_AN8        _SBF(0,0x03)  /* Reference is AN8 */

/***********************************************************************
 * ADC control bank high word register defines
 **********************************************************************/
/* ADC reference mask */
#define ADC_REF_MASK       _BITMASK(2)  
/* ADC negative input mask bit */
#define ADC_INM_MASK       _BIT(2)    
/* ADC negative input ground bit */
#define ADC_INM_GND        _BIT(2)    
/* ADC positive input mask */                                        
#define ADC_INP_MASK       _SBF(3,_BITMASK(4))
                                             
/* ADC settling time  mask */
#define ADC_STIME_MASK     _SBF(7,_BITMASK(9))
/* ADC control high bank settling time load macro */
#define ADC_SETTIME(n)     (((n) & 0x1FF) << 7)
/* ADC settling time bitfield width */
#define ADC_SETTIME_WIDTH   9  

/* ADC control high bank positive input MUX selection load macro */
#define ADC_INPSEL(n)      (((n) & 0xF) << 3)
/* ADC control high bank negative input MUX selection load macro */
#define ADC_INNSEL(n)      (((n) & 0x1) << 2)
/* ADC control high bank positive reference selection load macro */
#define ADC_REFP_SEL(n)    ((n) & 0x3)

/***********************************************************************
 * ADC control bank low word register defines
 **********************************************************************/

#define ADC_REF_VREFN      _SBF(0,0x00)  /* Reference is VREF- */
#define ADC_REF_AN1        _SBF(0,0x01)  /* Reference is AN1 */
#define ADC_REF_AN3        _SBF(0,0x02)  /* Reference is AN3 */
#define ADC_REF_AN9        _SBF(0,0x03)  /* Reference is AN9 */
/* ADC control low bank negative reference selection load macro */
#define ADC_REFN_SEL(n)    ((n) & 0x3)
/* ADC FET bit location for Analog 0 line pullup to VDDA */
#define ADC_FET_AN0_VDDA   _BIT(2)
/* ADC FET bit location for Analog 0 line pullup via 100K (penirq) */
#define ADC_FET_AN0_VDDA1K _BIT(12)
/* ADC FET bit location for Analog 1 line pullup to VDDA */
#define ADC_FET_AN1_VDDA   _BIT(3)
/* ADC FET bit location for Analog 1 line pulldown to GND */
#define ADC_FET_AN1_GND    _BIT(4)
/* ADC FET bit location for Analog 2 line pullup to VDDA */
#define ADC_FET_AN2_VDDA   _BIT(5)
/* ADC FET bit location for Analog 2 line pulldown to GND */
#define ADC_FET_AN2_GND    _BIT(6)
/* ADC FET bit location for Analog 3 line pulldown to GND */
#define ADC_FET_AN3_GND    _BIT(7)
/* ADC FET bit location for Analog 4 line pullup via 100K (penirq) */
#define ADC_FET_AN4_VDDA1K _BIT(13)
/* ADC FET bit location for Analog 4 line pulldown to GND */
#define ADC_FET_AN4_GND    _BIT(8)
/* ADC bias control bit mask */
#define ADC_BIASC_MASK     _SBF(2,_BITMASK(12)) 

/***********************************************************************