cstartup.s79

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.52 $
;
;-----------------------------------------------------------------------------
	
;
; Naming covention of labels in this file:
;
;  ?xxx	  - External labels only accessed from assembler.
;  __xxx  - External labels accessed from or defined in C.
;  xxx	  - Labels local to one module (note: this file contains
;           several modules).
;  main	  - The starting point of the user program.
;

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode
	

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------

		MODULE	?RESET
		COMMON	INTVEC:CODE:NOROOT(2)
		PUBLIC  __program_start
		EXTERN	?cstartup
		EXTERN	undef_handler, swi_handler, prefetch_handler
		EXTERN	data_handler, irq_handler, fiq_handler
		CODE32	; Always ARM mode after reset	
		org	0x00
__program_start
		ldr	pc,=?cstartup  ; Absolute jump can reach 4 GByte
;		ldr	b,?cstartup    ; Relative branch allows remap, limited to 32 MByte
		org	0x04
;		ldr	pc,=undef_handler
		org	0x08
;		ldr	pc,=swi_handler
		org	0x0c
;		ldr	pc,=prefetch_handler
		org	0x10
;		ldr	pc,=data_handler
		org	0x18
;		ldr	pc,=irq_handler
		org	0x1c
;		ldr	pc,=fiq_handler

		; Constant table entries (for ldr pc) will be placed at 0x20
		org	0x20
		LTORG
;		ENDMOD	__program_start
                ENDMOD


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
		MODULE	?CSTARTUP

		RSEG	IRQ_STACK:DATA(2)
		RSEG	SVC_STACK:DATA:NOROOT(2)
		RSEG	CSTACK:DATA(2)
		RSEG	ICODE:CODE:NOROOT(2)
		PUBLIC	?cstartup
		EXTERN	?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.


		CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
                mrs     r0,cpsr                             ; Original PSR value
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of IRQ_STACK

                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of CSTACK

#ifdef __ARMVFP__
; Enable the VFP coprocessor.
                mov     r0, #0x40000000                 ; Set EN bit in VFP
                fmxr    fpexc, r0                       ; FPEXC, clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
                mov     r0, #0x01000000		        ; Set FZ bit in VFP
                fmxr    fpscr, r0                       ; FPSCR, clear others.
#endif

; Add more initialization here


; Since we now have a stack, we can execute simple C code (no heap)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Initialize System, core and pheripheral clocks
    IMPORT  init_clocks, WEAK
init_system_clocks
    BL    init_clocks

; Initialize SDRAM and SRAM memory
    IMPORT  init_mem, WEAK
init_memory
    BL    init_mem

; Below code for MMU table initialization
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    	MOV 	r1, #0x70		;Disable MMU
   	MCR	p15, 0, r1, c1, c0, 0

MMU_TURN_ON		EQU		0x27F		;MMU enable,cache wb on,
SDRAM_BASE		EQU		(0x20000000)	;Base address for SDRAM
SDRAM_SIZE		EQU		(32*1024*1024)	;32M bytes of SDRAM
SDRAM_END		EQU		(SDRAM_BASE + SDRAM_SIZE)
; MMU translation table in 16K bytes below top of the memory
MMU_TRANS_TABLE	EQU		(SDRAM_END-16*1024)
    	
; Initialize the MMU table and enable the cache
    	IMPORT  init_mmu_table
	LDR	r0, = MMU_TRANS_TABLE
    	BL    	init_mmu_table

; Set up the Domain Access Control as all Manager
; Make all domains all open
    	LDR     r1,=0xFFFFFFFF
	MCR	p15, 0, r1, c3, c0, 0
;  Flush Unified TLB
        MOV     r1,#0x0
    	MCR	p15, 0, r1, c8, c7, 0
;  Invalidate ID Cache
	MCR	p15, 0, r1, c7, c7, 0
;  Set up TTB
    	LDR	r0,=MMU_TRANS_TABLE
	MCR	p15, 0, r0, c2, c0, 0
; Set up to jump to virtual location
; Startup code is in flash which is now mapped to 0x44000000
    	LDR	r3,= (entry + 0x44000000)
; Enable the MMU
;       MOV 	  r1, #0x71
        LDR 	  r1, = MMU_TURN_ON    ;enable cache, enable write buffer
    	MCR	  p15, 0, r1, c1, c0, 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Jump to the virtual address which is in R3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    	MOV	  pc, r3	; Jump to the virtual address which is in R3.
	NOP	  ; These NOP are in the pipeline and do nothing
    	NOP	  ; as they are executed.
	NOP
    	NOP
    	NOP
	NOP

; Continue to ?main for more IAR specific system startup
entry
    	IMPORT  __main, WEAK
    	BL    	__main

                ldr     r0,=?main
                bx      r0

                LTORG

                ENDMOD


                END