📄 lh79524_startup.s
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;***********************************************************************
; $Workfile: lh79524_startup.s $
; $Revision: 1.0 $
; $Author: ZhangJ $
; $Date: Oct 20 2004 09:41:34 $
;
; Project: LH79524
;
; Description: Boot code for the LH79524
; This code performs basic initialization of the LH79524. The
; code in this file does not make any assumptions about the board
; layout and memory map. It does not initialize the MMU. This code
; is meant to serve as an example for setting up the chip to a basic
; state from which advanced, board dependent initialization can be
; subsequently performed. For an example of advanced initialization,
; consult the appropriate BSP.
; The basic startup code does the following:
; 1. Set up default handlers for the ARM exception vectors.
; 2. Allow room for the FIQ handler to be placed inline.
; 3. In the default Reset handler, first ensure that the MMU is
; disabled and cleared, in case
; we got here by a jump to zero.
; 4. Set up a "boot status" area at the top of Internal RAM. Save the
; boot status there.
; 5. Set up a "save status" area at the top of Internal RAM, below the
; boot status area.
; 6. Mask interrupts at the core and at the VIC.
; 7. Initialize the stack pointer for all ARM modes at the top of
; internal SRAM below the save status area.
; 8. Initialize CPU, system and pheripheral clocks.
; 9. Perform SRAM and SDRAM initialization if such code is provided.
; 10. Jump to the advanced initialization code (c_entry) if it is
; provided, else spin.
; A default exception handler is provided for the ARM abort modes.
; This handler saves system state in the save status area and executes
; a fault_spin routine if such code is provided, else it spins. It is
; recommended that a fault spin routine be linked in which provides
; some visual indication that a fault has occurred.
;
; I M P O R T A N T
; -----------------
; If the extended startup code (c_entry/__main/init_mem) is included
; in the build, ensure that the Linker is instructed not to remove
; unused sections. This is done by using the linker command line:
; -remove (dbg)
;
; $Log:: //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/$
;
; Rev 1.0 Oct 20 2004 09:41:34 ZhangJ
; Initial revision.
;
; Rev 1.2 Jul 20 2004 16:50:50 PattamattaD
; Updated comments.
;
; Rev 1.1 Jun 15 2004 14:10:00 PattamattaD
; include hearder name changed.
;
; Rev 1.0 Jun 15 2004 14:03:24 PattamattaD
; Initial revision.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (c) 2004 Sharp Microelectronics of the Americas
;
; All rights reserved
;
; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
;
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This code performs all the initialization required before
; branching to the main C application code. It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code.
AREA | !bootlh79524|, CODE, READONLY ; name this block of code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Placing the blankspace character ' ' and the exclamation character '!'
; in front of the area name BootLH79524 ensures that this area is
; placed at the beginning of the image even if it is not specified
; explicitly in the ARM linker settings.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; LH79524 Definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
INCLUDE lh79524_startup.i
; IOCON related register definition
IOCON_REG_BASE EQU (0xfffe5000)
MUX_7_OFFSET EQU 0x30
MUX_10_OFFSET EQU 0x48
MUX_11_OFFSET EQU 0x50
MUX_12_OFFSET EQU 0x58
MUX_19_OFFSET EQU 0x90
MUX_20_OFFSET EQU 0x98
PIN_MUX_CONSTANT EQU 0x5555
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;*********** The RESET entry point ***********
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This MCU reset from physical memory 0x0
; Flash memory is normally put here
; ARM exception (interruption vector) table is located here
; 0x0 Reset
; 0x4 Undefined instruction
; 0x8 Software interrupt
; 0xc Prefetch Abort
; 0x10 Data Abort
; 0x18 IRQ (Interrupt)
; 0x1c FIQ (Fast Interrupt)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
EXPORT Rom_Start
ENTRY
Rom_Start
; Exception vector table
B Reset_Handler
B Undefined_Handler ; 0x04
B SWI_Handler ; 0x08
B Prefetch_Handler ; 0x0C
B Abort_Handler ; 0x10
NOP ; Reserved vector
LDR pc, [pc, #-0xFF0] ; 0x18 instruction to invoke VIC for IRQ
B FIQ_Handler ; 0x1C
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; The following handlers save status if possible
; See Save_Status comments for locations in IRAM of saved status.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Undefined_Handler
MOV r7, pc
B Save_Status
SWI_Handler
MOV r7, pc
B Save_Status
Prefetch_Handler
MOV r7, pc
B Save_Status
Abort_Handler
MOV r7, pc
B Save_Status
IRQ_Handler
MOV r7, pc
B Save_Status
FIQ_Handler
MOV r7, pc
B Save_Status
Reset_Handler
; Disable the MMU
MOV r1, #MMU_CONTROL_RESET
MCR p15, 0, r1, c1, c0, 0
; set SVC mode
mov r0, #(MODE_SVC :OR: I_Bit :OR: F_Bit)
msr cpsr_cxsf,r0
nop
; Disable the interruption
ldr r1,=VIC_REG_BASE
mov r0,#0
str r0,[r1,#VIC_INTENC_OFFSET]
mvn r0, #1
str r0,[r1,#VIC_SOFT_INTC_OFFSET]
; Set up pin mux for correct memory access as D0 to D31 and A16 to A23
ldr r1, =IOCON_REG_BASE
ldr r0,=PIN_MUX_CONSTANT ;set D25 to D21 and D15 to D13
str r0,[r1,#MUX_10_OFFSET]
ldr r0,=PIN_MUX_CONSTANT ;set D20 to D17 and D12 to D9
str r0,[r1,#MUX_11_OFFSET]
ldr r0,=0x5000 ;set D16 and D8
str r0,[r1,#MUX_12_OFFSET]
ldr r0,=0x1110 ;set D26 to D28
str r0,[r1,#MUX_20_OFFSET]
ldr r0,=0x441 ;set D29 to D31
str r0,[r1,#MUX_19_OFFSET]
ldr r0, =PIN_MUX_CONSTANT ;set A23 to A16
str r0,[r1,#MUX_7_OFFSET]
; Initialize the stacks in IRAM for all modes, user app can redefine
init_stacks
;All interrupts disabled at core
MOV r1, #I_Bit :OR: F_Bit ; No Interrupts
; Enter IRQ mode and setup the IRQ stack pointer
ORR r0, r1, #MODE_IRQ
MSR cpsr_cxsf, r0
LDR r13, =IRQ_STACK_BASE
; Enter FIQ mode and setup the FIQ stack pointer
ORR r0, r1, #MODE_FIQ
MSR cpsr_cxsf, r0
LDR r13, =FIQ_STACK_BASE
; Enter Abort mode and setup the Abort stack pointer
ORR r0, r1, #MODE_ABT
MSR cpsr_cxsf, r0
LDR r13, =ABORT_STACK_BASE
; Enter Undefined mode and setup the Undefined stack pointer
ORR r0, r1, #MODE_UNDEF
MSR cpsr_cxsf, r0
LDR r13, =UNDEF_STACK_BASE
; Enter System mode and setup the User/System stack pointer
ORR r0, r1, #MODE_SYS
MSR cpsr_cxsf, r0
LDR r13, =SYSTEM_STACK_BASE
; Enter SVC mode and setup the SVC stack pointer.
; This is the mode for runtime initialization.
ORR r0, r1, #MODE_SVC
MSR cpsr_cxsf, r0
LDR r13, =SVC_STACK_BASE
; Since we now have a stack, we can execute simple C code (no heap)
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Initialize System, core and pheripheral clocks
IMPORT init_clocks
init_system_clocks
BL init_clocks
; Initialize SDRAM and SRAM memory
IMPORT init_mem
init_memory
BL init_mem
; Below code for MMU table initialization
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOV r1, #0x70 ;Disable MMU
MCR p15, 0, r1, c1, c0, 0
MMU_TURN_ON EQU 0x27F ;MMU enable,cache wb on,
SDRAM_BASE EQU (0x20000000) ;Base address for SDRAM
SDRAM_SIZE EQU (32*1024*1024) ;32M bytes of SDRAM
SDRAM_END EQU (SDRAM_BASE + SDRAM_SIZE)
; MMU translation table in 16K bytes below top of the memory
MMU_TRANS_TABLE EQU (SDRAM_END-16*1024)
; Initialize the MMU table and enable the cache
IMPORT init_mmu_table
LDR r0, = MMU_TRANS_TABLE
BL init_mmu_table
; Set up the Domain Access Control as all Manager
; Make all domains all open
MOV r1,#0xFFFFFFFF
MCR p15, 0, r1, c3, c0, 0
; Flush Unified TLB
MOV r1,#0x0
MCR p15, 0, r1, c8, c7, 0
; Invalidate ID Cache
MCR p15, 0, r1, c7, c7, 0
; Set up TTB
LDR r0,=MMU_TRANS_TABLE
MCR p15, 0, r0, c2, c0, 0
; Set up to jump to virtual location
; Startup code is in flash which is now mapped to 0x44000000
LDR r3,= (entry + 0x44000000)
; Enable the MMU
; MOV r1, #0x71
LDR r1, = MMU_TURN_ON ;enable cache, enable write buffer
MCR p15, 0, r1, c1, c0, 0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Jump to the virtual address which is in R3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOV pc, r3 ; Jump to the virtual address which is in R3.
NOP ; These NOP are in the pipeline and do nothing
NOP ; as they are executed.
NOP
NOP
NOP
NOP
; If this is built with c_entry or main(), jump to it
IMPORT c_entry, WEAK
IMPORT __main, WEAK
entry
BL c_entry
BL __main
; If above subroutine ever returns, just sit in an endless loop
B .
EXPORT main ; defined to ensure C runtime lib is not linked in
main ; defined to ensure C runtime lib is not linked in
;-----------------------------------------------------------------------
;
; Function: Save_Status
;
; Purpose:
; Saves the system status registers in internal RAM on an exception
; for retrieval and analysis by a debugger
;
; Processing:
; Save the exception mode Link Register, Stack Pointer, CPSR, SPSR,
; general purpose registers and CP15 registers at the top of IRAM.
; Set up a stack and branch to a fault_spin function if provided.
; Else, spin in an infinite loop (branch-to-self).
;
; Parameters: None
;
; Outputs: None
;
; Returns: Nothing
;
; Notes:
; Save_Status Memory Map, near top of IRAM
; Save_Status written to fixed location starting downward from
; SAVE_STATUS_STORE_ADDR
; 0x60003FEC Exception mode LR
; 0x60003FE8 Exception mode SP
; 0x60003FE4 Exception mode CPSR
; 0x60003FE0 Exception mode SPSR
; 0x60003FDC-0xB0013FAC r12 through r0 in that order
; 0x60003FA8 MMU Control Register value
; 0x60003FA4 MMU TTB
; 0x60003FA0 MMU FSR
; 0x60003F9C MMU FAR
; 0x60003F98 MMU DAC
; 0x60003F94 Faulting mode LR
; 0x60003F90 Faulting mode SP
; 0x60003F8C Faulting mode SPSR (if Fault mode not User or System)
;-----------------------------------------------------------------------
Save_Status
mov r12, r13 ; save current SP (ip destroyed)
ldr r13, =SAVE_STATUS_STORE_ADDR ; create current stack in IRAM
stmdb r13!, {r12, r14} ; store current mode SP,LR
mrs r14, cpsr ; get current mode CPSR
stmdb r13!, {r14} ; store current mode CPSR
mrs r14, spsr ; get current mode SPSR
stmdb r13!, {r14} ; store current mode SPSR
stmdb r13!, {r0-r12} ; store r0-r12
;get MMU Control Register
mrc MMU_CP, 0, r14, MMU_REG_CONTROL, c0, 0
stmdb r13!, {r14} ;store MMU Control Register
;get MMU TTB
mrc MMU_CP, 0, r14, MMU_REG_TTB, c0, 0
stmdb r13!, {r14} ;store MMU TTB
;get MMU FSR
mrc MMU_CP, 0, r14, MMU_REG_FS, c0, 1
stmdb r13!, {r14} ;store MMU FSR
;get MMU FAR
mrc MMU_CP, 0, r14, MMU_REG_FA, c0, 0
stmdb r13!, {r14} ;store MMU FAR
;get MMU DAC
mrc MMU_CP, 0, r14, MMU_REG_DAC, c0, 0
stmdb r13!, {r14} ;store MMU DAC
mrs r14, spsr ; get current mode SPSR again
mvn r12, #0x1F
bics r0, r14, r12
cmp r0, #MODE_USR
orreq r14, r14, #MODE_SYS
orr r14, r14, #I_Bit:OR:F_Bit ; Mask Interrupts in fault mode
bic r14, r14, #T_Bit ; Ensure ARM mode, not Thumb
mov r1, r13 ; store SP in r1
msr cpsr_c, r14 ;switch back to faulting mode
stmdb r1!, {r14} ;store faulting mode LR
stmdb r1!, {r13} ;store faulting mode SP
cmp r0, #MODE_SYS
mrsne r14, spsr ;get faulting mode SPSR
stmnedb r1!, {r14} ;store faulting mode SPSR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Set up a valid stack pointer for calls, call fault_spin, and
; spin.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IMPORT fault_spin, WEAK
; Enter SVC mode, ARM Mode, no interrupts,
; and setup the SVC stack pointer in Internal SRAM
mov r0, #(MODE_SVC :OR: I_Bit :OR: F_Bit) ; No Interrupts
msr cpsr_c, r0
ldr r13, =IRAM_SVC_STACK_BASE
bl fault_spin
b .
END
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