sdk79524_startup.c

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/* map physical at 0x4800,0000- Controled by CS2
 to virtual memory 0x4800,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x48000000, 0x48000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x4C00,0000- Controled by CS3
 to virtual memory 0x4C00,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x4C000000, 0x4C000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x5000,0000- Controled by CS4
 to virtual memory 0x5000,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x50000000, 0x50000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x5400,0000- Controled by CS5
 to virtual memory 0x5400,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x54000000, 0x54000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x5800,0000- Controled by CS6
 to virtual memory 0x5800,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x58000000, 0x58000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

    {0, 0, 0, 0}  // Marks end of initialization array.  Required! 
};


/***********************************************************************
*
* Function: init_mmu_table
*
* Purpose: Initialize MMU table 
*
* Parameters: None.
*
* Outputs: None.
*
* Returns: None.
*
* Notes: None.
**********************************************************************/
/* mmu table must be on a 16K boundary */
#define MMU_TABLE_ADDR	(0x60004000) /* MMU table in internal SRAM */

void init_mmu_table(UNS_32 mmu_table_addr)
{
    UNS_32 *uiptr;
    UNS_32 *tt = (UNS_32 *)mmu_table_addr;
    UNS_32 idx;
    UNS_32 va_idx;
    UNS_32 pa_addr;
    TT_SECTION_BLOCK_T *ttsbp = tt_init_basic;
    
     /*******************************************************************
     * Clear the entire Translation Table.
     * This results in L1D_TYPE_FAULT being the default for any
     * uninitialized entries.
     ******************************************************************/
    uiptr = (UNS_32 *) mmu_table_addr;
    for (idx = 0; idx < MMU_TT_ENTRIES; idx++)
        *uiptr++ = MMU_L1D_TYPE_FAULT;

    /* Build the translation table from user provided
       TT_SECTION_BLOCK_TYPE array */
    while (ttsbp->num_sections != 0)
    {
        switch ((ttsbp->entry) & MMU_L1D_TYPE_PG_SN_MASK)
        {
            case MMU_L1D_TYPE_SECTION:
                va_idx = ttsbp->virt_addr >> 20;
                pa_addr = ttsbp->phys_addr & MMU_L2D_SN_BASE_MASK;
                for (idx = 0; idx < ttsbp->num_sections; idx++)
                {
                    *(tt + va_idx) = (pa_addr | ttsbp->entry);
                    va_idx++;
                    pa_addr += 0x100000;
                }
                break;

            default:
                break;
        }

        ttsbp++;
    }

}

/***********************************************************************
* Function: init_sdram
*
* Purpose: To initialize SDRAM on the EVB79524 hardware
*
* Description: 
*   Two memory banks comprising of two 4Mbit x 16 SDRAM chips
*   64 MBytes total.
*
* nSDCE0 - 32MB at 0x20000000 (SDRAM Bank0 Base)
* nSDCE1 - 32MB at 0x30000000 (SDRAM Bank1 Base)
*
*  ***** Micron Initialization Sequence from their data sheet
*        for the Micron MT48LC16FFG 8Mb x 16 SDRAM chip:
*
*  Initialization
*
*  SDRAMs must be powered up and initialized in a
*  predefined manner. Operational procedures other than
*  those specified may result in undefined operation. Once
*  power is applied to VDD and VDDQ (simultaneously) and
*  the clock is stable (stable clock is defined as a signal
*  cycling within timing constraints specified for the clock
*  pin), the SDRAM requires a 100祍 delay prior to issuing
*  any command other than a COMMAND INHIBIT or NOP.
*
*  Starting at some point during this 100祍 period and
*  continuing at least through the end of this period,
*  COMMAND INHIBIT or NOP commands should be applied.
*  Once the 100祍 delay has been satisfied with at least
*  one COMMAND INHIBIT or NOP command having been applied,
*  a PRECHARGE command should be applied. All banks must
*  then be precharged, thereby placing the device in the
*  all banks idle state.
*
*  Once in the idle state, two AUTO REFRESH cycles
*  must be performed. After the AUTO REFRESH cycles are
*  complete, the SDRAM is ready for mode register programming.
*
*  Because the mode register will power up in an
*  unknown state, it should be loaded prior to applying any
*  operational command.
*
* *****  The JEDEC recommendation for initializing SDRAM is:
*
*  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
*  Wait 200uS
*  PRECHARGE all
*  8 AUTO REFRESH COMMANDS
*  LOAD MODE REGISTER
*  SDRAM is ready for operation
*
* *****  The Micron SDRAM parts will work fine with the JEDEC sequence,
*  but also allow for a quicker init sequence of:
*
*  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
*  Wait at least 100uS (during which time start applying and
*     continue applying NOP or COMMAND INHIBIT)
*  PRECHARGE all
*  2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
*  LOAD MODE REGISTER
*  SDRAM is ready for operation
*
*  Notes:  The order of the AUTO REFRESH commands and LOAD MODE
*          REGISTER can be reversed if preferred.
*          User should stop watchdog timer and disable caches and MMU's
*          before calling this function.
*
**********************************************************************/
void init_sdram_16bit(void)
{
  UNS_32 tmp;
  UNS_64 current_hclk;
  
  current_hclk = RCPC_GET_HCLK(EVB79524_XTAL_IN);
  timer_wait_us(TIMER1, 100, EVB79524_XTAL_IN);
  
  /* Set command delay startergy */
  EMC->sdramc_read_config = EMC_SDRAMC_RDCFG_CMDDELAY_STG;
  
  /* configure "device config register" nSDCE0-1 for proper width
     SDRAM */
  EMC->sdramc_cfg0 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 /*| EMC_SDRAMC_CFG_BUF_EN*/;
  
  EMC->sdramc_rascas0 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  EMC->sdramc_cfg1 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 /*| EMC_SDRAMC_CFG_BUF_EN*/;
  
  EMC->sdramc_rascas1 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  /* min 20ns program 1 so that atleast 2 HCLKs are used */
  EMC->sdramc_rp   = EMC_SDRAMC_TRP(EVB79524_SDRAM_TRP,current_hclk);
  EMC->sdramc_ras  = EMC_SDRAMC_TRAS(EVB79524_SDRAM_TRAS,current_hclk);
  EMC->sdramc_srex = EMC_SDRAMC_TSREX(EVB79524_SDRAM_TREX,current_hclk);
  EMC->sdramc_apr  = EMC_SDRAMC_TARP(EVB79524_SDRAM_TARP,current_hclk);
  EMC->sdramc_dal  = EMC_SDRAMC_TDAL(EVB79524_SDRAM_TDAL,current_hclk);
  EMC->sdramc_wr   = EMC_SDRAMC_TWR(EVB79524_SDRAM_TWR,current_hclk);
  EMC->sdramc_rc   = EMC_SDRAMC_TRC(EVB79524_SDRAM_TRC,current_hclk);
  EMC->sdramc_rfc  = EMC_SDRAMC_TRFC(EVB79524_SDRAM_TRFC,current_hclk);
  EMC->sdramc_xsr  = EMC_SDRAMC_TXSR(EVB79524_SDRAM_TXSR,current_hclk);
  EMC->sdramc_rrd  = EMC_SDRAMC_TRRD(EVB79524_SDRAM_TRRD,current_hclk);
  EMC->sdramc_mrd  = EMC_SDRAMC_TMRD(EVB79524_SDRAM_TMRD,current_hclk);
  
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS;
  
  timer_wait_us(TIMER1, 100, EVB79524_XTAL_IN);
  
  /* issue continuous NOP commands (INIT & MRS set) */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_NOP_CMD;
  
  /* load ~200us delay value to timer1 */
  timer_wait_us(TIMER1, 200, EVB79524_XTAL_IN);
  
  /* issue a "pre-charge all" command */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_PALL_CMD;
  
  /*******************************************************************
  * Minimum refresh pulse interval (tRFC) for MT48LC16LFFG=80nsec,
  * 100nsec provides more than adequate interval. 
  ******************************************************************/
  EMC->sdramc_refresh = EMC_SDRAMC_REFRESH(EVB79524_SDRAM_REFRESH,
                                           current_hclk);
  
  /* load ~250us delay value to timer1 */
  timer_wait_us(TIMER1, 250, EVB79524_XTAL_IN);
  
  /*******************************************************************
  *  Recommended refresh interval for normal operation of the Micron
  * MT48LC16LFFG = 7.8125usec (128KHz rate).
  * ((HCLK / 128000) - 1) = refresh counter interval rate, (subtract
  * one for safety margin).
  ******************************************************************/
  EMC->sdramc_refresh = EMC_SDRAMC_REFRESH(EVB79524_SDRAM_OPER_REFRESH,
                                           current_hclk);
  
  /* select mode register update mode */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_MODE_CMD;
  
  /*******************************************************************
  * Program the SDRAM internal mode registers on bank nSDCE0, 1, & 3
  * and reconfigure the SDRAM chips.  Bus speeds up to 50MHz
  * requires use of a CAS latency = 2.
  * To get correct value on address bus CAS cycle, requires a shift
  * by 11 for 32bit mode
  ******************************************************************/
  tmp = *((UNS_32 *)(EMC_SDRAMC_DCS0_BASE | _SBF(11, 0x23)));
  
  EMC->sdramc_cfg0 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 | EMC_SDRAMC_CFG_BUF_EN;
  
  EMC->sdramc_rascas0 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  tmp = *((UNS_32 *)(EMC_SDRAMC_DCS1_BASE | _SBF(11, 0x23)));
  
  EMC->sdramc_cfg1 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 | EMC_SDRAMC_CFG_BUF_EN;
  
  EMC->sdramc_rascas1 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  /* select normal operating mode */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_NORMAL_CMD;
  
  EMC->sdramc_cfg0 |= EMC_SDRAMC_CFG_BUF_EN;
  EMC->sdramc_cfg1 |= EMC_SDRAMC_CFG_BUF_EN;
}