sdk79524_startup.c

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

*
*  Starting at some point during this 100祍 period and
*  continuing at least through the end of this period,
*  COMMAND INHIBIT or NOP commands should be applied.
*  Once the 100祍 delay has been satisfied with at least
*  one COMMAND INHIBIT or NOP command having been applied,
*  a PRECHARGE command should be applied. All banks must
*  then be precharged, thereby placing the device in the
*  all banks idle state.
*
*  Once in the idle state, two AUTO REFRESH cycles
*  must be performed. After the AUTO REFRESH cycles are
*  complete, the SDRAM is ready for mode register programming.
*
*  Because the mode register will power up in an
*  unknown state, it should be loaded prior to applying any
*  operational command.
*
* *****  The JEDEC recommendation for initializing SDRAM is:
*
*  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
*  Wait 200uS
*  PRECHARGE all
*  8 AUTO REFRESH COMMANDS
*  LOAD MODE REGISTER
*  SDRAM is ready for operation
*
* *****  The Micron SDRAM parts will work fine with the JEDEC sequence,
*  but also allow for a quicker init sequence of:
*
*  APPLY POWER (Vdd/Vddq equally, and CLK is stable)
*  Wait at least 100uS (during which time start applying and
*     continue applying NOP or COMMAND INHIBIT)
*  PRECHARGE all
*  2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
*  LOAD MODE REGISTER
*  SDRAM is ready for operation
*
*  Notes:  The order of the AUTO REFRESH commands and LOAD MODE
*          REGISTER can be reversed if preferred.
*          User should stop watchdog timer and disable caches and MMU's
*          before calling this function.
*
**********************************************************************/
void init_sdram(void)
{
  UNS_32 tmp;
  UNS_64 current_hclk;
  
  current_hclk = RCPC_GET_HCLK(EVB79524_XTAL_IN);
  timer_wait_us(TIMER1, 100, EVB79524_XTAL_IN);
  
  /* Set command delay startergy */
  EMC->sdramc_read_config = EMC_SDRAMC_RDCFG_CMDDELAY_STG;
  
  /* configure "device config register" nSDCE0-1 for proper width
     SDRAM */
  EMC->sdramc_cfg0 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 /*| EMC_SDRAMC_CFG_BUF_EN*/;
  
  EMC->sdramc_rascas0 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  EMC->sdramc_cfg1 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 /*| EMC_SDRAMC_CFG_BUF_EN*/;
  
  EMC->sdramc_rascas1 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  /* min 20ns program 1 so that atleast 2 HCLKs are used */
  EMC->sdramc_rp   = EMC_SDRAMC_TRP(EVB79524_SDRAM_TRP,current_hclk);
  EMC->sdramc_ras  = EMC_SDRAMC_TRAS(EVB79524_SDRAM_TRAS,current_hclk);
  EMC->sdramc_srex = EMC_SDRAMC_TSREX(EVB79524_SDRAM_TREX,current_hclk);
  EMC->sdramc_apr  = EMC_SDRAMC_TARP(EVB79524_SDRAM_TARP,current_hclk);
  EMC->sdramc_dal  = EMC_SDRAMC_TDAL(EVB79524_SDRAM_TDAL,current_hclk);
  EMC->sdramc_wr   = EMC_SDRAMC_TWR(EVB79524_SDRAM_TWR,current_hclk);
  EMC->sdramc_rc   = EMC_SDRAMC_TRC(EVB79524_SDRAM_TRC,current_hclk);
  EMC->sdramc_rfc  = EMC_SDRAMC_TRFC(EVB79524_SDRAM_TRFC,current_hclk);
  EMC->sdramc_xsr  = EMC_SDRAMC_TXSR(EVB79524_SDRAM_TXSR,current_hclk);
  EMC->sdramc_rrd  = EMC_SDRAMC_TRRD(EVB79524_SDRAM_TRRD,current_hclk);
  EMC->sdramc_mrd  = EMC_SDRAMC_TMRD(EVB79524_SDRAM_TMRD,current_hclk);
  
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS;
  
  timer_wait_us(TIMER1, 100, EVB79524_XTAL_IN);
  
  /* issue continuous NOP commands (INIT & MRS set) */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_NOP_CMD;
  
  /* load ~200us delay value to timer1 */
  timer_wait_us(TIMER1, 200, EVB79524_XTAL_IN);
  
  /* issue a "pre-charge all" command */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_PALL_CMD;
  
  /*******************************************************************
  * Minimum refresh pulse interval (tRFC) for MT48LC16LFFG=80nsec,
  * 100nsec provides more than adequate interval. 
  ******************************************************************/
  EMC->sdramc_refresh = EMC_SDRAMC_REFRESH(EVB79524_SDRAM_REFRESH,
                                           current_hclk);
  
  /* load ~250us delay value to timer1 */
  timer_wait_us(TIMER1, 250, EVB79524_XTAL_IN);
  
  /*******************************************************************
  *  Recommended refresh interval for normal operation of the Micron
  * MT48LC16LFFG = 7.8125usec (128KHz rate).
  * ((HCLK / 128000) - 1) = refresh counter interval rate, (subtract
  * one for safety margin).
  ******************************************************************/
  EMC->sdramc_refresh = EMC_SDRAMC_REFRESH(EVB79524_SDRAM_OPER_REFRESH,
                                           current_hclk);
  
  /* select mode register update mode */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_MODE_CMD;
  
  /*******************************************************************
  * Program the SDRAM internal mode registers on bank nSDCE0, 1, & 3
  * and reconfigure the SDRAM chips.  Bus speeds up to 50MHz
  * requires use of a CAS latency = 2.
  * To get correct value on address bus CAS cycle, requires a shift
  * by 11 for 32bit mode
  ******************************************************************/
  tmp = *((UNS_32 *)(EMC_SDRAMC_DCS0_BASE | _SBF(11, 0x22)));
  
  EMC->sdramc_cfg0 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 | EMC_SDRAMC_CFG_BUF_EN;
  
  EMC->sdramc_rascas0 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  tmp = *((UNS_32 *)(EMC_SDRAMC_DCS1_BASE | _SBF(11, 0x22)));
  
  EMC->sdramc_cfg1 = /*EMC_SDRAMC_CFG_LOW_PWR_MD | */
    SDRAMC_32LP_8Mx16_4B_R12_C9 | EMC_SDRAMC_CFG_BUF_EN;
  
  EMC->sdramc_rascas1 = EMC_SDRAMC_RASCAS_RAS3 | 
    EMC_SDRAMC_RASCAS_CAS2;
  
  /* select normal operating mode */
  EMC->sdramc_ctrl = EMC_SDRAMC_CTL_CE | EMC_SDRAMC_CTL_CS | 
    EMC_SDRAMC_CTL_NORMAL_CMD;
  
  EMC->sdramc_cfg0 |= EMC_SDRAMC_CFG_BUF_EN;
  EMC->sdramc_cfg1 |= EMC_SDRAMC_CFG_BUF_EN;
}

/***********************************************************************
*
* Function: init_ioconfig
*
* Purpose: Initialize IO Configuration registers 
*
* Parameters: None.
*
* Outputs: None.
*
* Returns: None.
*
* Notes: None.
**********************************************************************/
void init_ioconfig(void)
{

  /*EVB79524 has 16 bit NOR flash boot chip. Hence the inetreface comes
   in 16bit mode so enable upper 16bits of data bus*/
  IOCON->mux_ctl_12 = IOCON_MUX12_D8 | IOCON_MUX12_D16;
  IOCON->mux_ctl_11 = IOCON_MUX11_D9 | IOCON_MUX11_D10 | IOCON_MUX11_D11
   | IOCON_MUX11_D12 | IOCON_MUX11_D17 | IOCON_MUX11_D18 
   | IOCON_MUX11_D19 | IOCON_MUX11_D20;
  IOCON->mux_ctl_10 = IOCON_MUX10_D13 | IOCON_MUX10_D14 | IOCON_MUX10_D15
   | IOCON_MUX10_D21 | IOCON_MUX10_D22 | IOCON_MUX10_D23 
   | IOCON_MUX10_D24 | IOCON_MUX10_D25;
  IOCON->mux_ctl_20 = IOCON_MUX20_D26 | IOCON_MUX20_D27 | IOCON_MUX20_D28;
  IOCON->mux_ctl_19 = IOCON_MUX19_D29 | IOCON_MUX19_D30 | IOCON_MUX19_D31;

  IOCON->mux_ctl_7 = IOCON_MUX7_A16 | IOCON_MUX7_A17 | IOCON_MUX7_A18
                    | IOCON_MUX7_A19 | IOCON_MUX7_A20 | IOCON_MUX7_A21
                    | IOCON_MUX7_A22 | IOCON_MUX7_A23;
}


/***********************************************************************
 * UNS_32 num_sections: number of 1MByte sections >=1 for all blocks
 *     except last; last = 0
 * UNS_32 virt_addr: as required, base Virtual address for block
 * UNS_32 phys_addr: as required, PT address or Section address
 * UNS_32 entry is composed of the following 'or'd' together:
 *     access_perm:  MMU_L1D_AP_x (x = SVC_ONLY, USR_RO, ALL)
 *     domain:   MMU_L1D_DOMAIN(n) as applicable
 *     cacheable:  MMU_L1D_CACHEABLE if applicable
 *     write_buffered:  MMU_L1D_BUFFERABLE if applicable
 *     descriptor_type: MMU_L1D_TYPE_x (x = FAULT, PAGE, SECTION)
 **********************************************************************/
typedef const struct
{
    UNS_32 num_sections; /* Number of 1MByte sections */
    UNS_32 virt_addr;    /* Virtual address of section */
    UNS_32 phys_addr;    /* Physical address of section */
    /* Section attributes - an 'OR'ed combination of MMU_L1D_AP_x,
       MMU_L1D_DOMAIN, MMU_L1D_CACHEABLE,
       MMU_L1D_BUFFERABLE, and MMU_L1D_TYPE_x */
    UNS_32 entry;
} TT_SECTION_BLOCK_T;

/* Definition for MMU control bits */

/* Number of entries in MMU Translation table */ 
#define MMU_TT_ENTRIES          4096
/* Size of the MMU Translation table */ 
#define MMU_TT_SIZE             (MMU_TT_ENTRIES * 4)
/* MMU level 1 compatibility bit */
#define MMU_L1D_TYPE_PG_SN_MASK 0x00000003
/* MMU level 2 large page address mask */
#define MMU_L2D_SN_BASE_MASK    0xFFF00000
/* Level 1 Descriptor fields */
/* MMU MMU level 1 invalid page or section identifier */
#define MMU_L1D_TYPE_FAULT      0x00000000
/* MMU MMU level 1 page or section identifier */
#define MMU_L1D_BUFFERABLE      0x00000004
/* MMU MMU level 1 page or section cacheable bit */
#define MMU_L1D_CACHEABLE       0x00000008
/* MMU MMU level 1 page or section domain load macro */
#define MMU_L1D_DOMAIN(n)       _SBF(5, ((n) & 0x0F))
/* MMU MMU level 1 section all access bit */
#define MMU_L1D_AP_ALL          0x00000C00
/* MMU MMU level 1 1MByte section identifier */
#define MMU_L1D_TYPE_SECTION    0x00000002


/* LH79524 MMU virtual mapping table */

TT_SECTION_BLOCK_T tt_init_basic[] = {

/* map physical SDRAM at 0x2000,0000-0x21FF,FFFF 
  to virtual memory 0x0000,0000-0x01FF,FFFF
  32M bytes of addressing, 32 entry in the MMU table	
  cache off, write buffer off
  */
    {32, 0x00000000, 0x20000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_TYPE_SECTION)},

/* map physical SDRAM at 0x2000,0000-0x21FF,FFFF 
 to virtual memory 0x2000,0000-0x21FF,FFFF
 32M bytes of addressing, 32 entry in the MMU table	
 cache on, write buffer on
*/
    {32, 0x20000000, 0x20000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},
        
/* map internal peripheral at 0xFFF0,0000-
 to virtual memory 0xFFF0,0000-
 1M bytes of addressing, 1 entry in the MMU table	
 cache off, write buffer off  
*/
    {1, 0xFFF00000, 0xFFF00000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_TYPE_SECTION)},
 
/* map internal SRAM at 0x6000,0000-
 to virtual memory 0x6000,0000-
 1M bytes of addressing, 1 entry in the MMU table	
 cache on, write buffer on
*/
    {1, 0x60000000, 0x60000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x4000,0000- Controled by CS0
 to virtual memory 0x4000,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x40000000, 0x40000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},

/* map physical at 0x4400,0000- Controled by CS1
 to virtual memory 0x4400,0000-
 16M bytes of addressing, 16 entry in the MMU table	
 cache on, write buffer on
*/
    {16, 0x44000000, 0x44000000, 
        (MMU_L1D_AP_ALL | MMU_L1D_DOMAIN(0) |
        MMU_L1D_CACHEABLE | MMU_L1D_BUFFERABLE |
        MMU_L1D_TYPE_SECTION)},