sdk79524_startup.c

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/***********************************************************************
 * $Workfile:   evb79524_startup.c  $
 * $Revision:   1.0  $
 * $Author:   LiJ  $
 * $Date:   Aug 31 2004 16:41:54  $
 *
 * Project: Spectre Phase 1
 *
 * Description: Startup code for the Spectre phase 1 hardware.
 *      Initializes memory, sets up the MMU, stacks, etc.
 *
 * Local Includes:
 *
 * Revision History:
 * $Log::   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps$
 * 
 *    Rev 1.0   Aug 31 2004 16:41:54   LiJ
 * Initial revision.
 * 
 *    Rev 1.2   Jul 20 2004 16:51:18   PattamattaD
 * Updated comments.
 * 
 *    Rev 1.1   Jun 25 2004 13:59:06   PattamattaD
 * Modified memory init.
 * 
 *    Rev 1.0   Jun 15 2004 14:11:38   PattamattaD
 * Initial revision.
 * 
 * 
 * 
 ***********************************************************************
 * 
 *  Copyright (c) 2004 Sharp Microelectronics of the Americas 
 * 
 *  All rights reserved 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
 * 
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
 * 
 **********************************************************************/

#include "sdk79524_board.h"
#include "lh79524_rcpc.h"
#include "lh79524_emc.h"
#include "lh79524_iocon.h"
#include "lh79524_gpio.h"
#include "lh79524_timer_driver.h"

/* forward declarations */
void fault_spin(void);
void init_mem(void);
void init_clocks(void);
static void init_smc(void);
static void init_sdram(void);
static void init_ioconfig(void);

/***********************************************************************
*
* Function: fault_spin
*
* Purpose: 
*  Provide a visual annunciator for a fault condition.
*
* Processing: 
*  Rapidly toggle LEDs LED_GPIOA_D8 and LED_GPIOA_D11 on the board.
*
* Parameters: None
*
* Outputs: None
*
* Returns: None
*
* Notes: None
*  
**********************************************************************/
void fault_spin(void)
{
  /* select PA1 and PA0 muxed signals */
  IOCON->mux_ctl_5 &= IOCON_MUX_MASK(IOCON_RES5_PA1_INT3_UARTTX2_UARTIRTX2);
  IOCON->mux_ctl_5 &= IOCON_MUX_MASK(IOCON_RES5_PA0_INT2_UARTRX2_UARTIRRX2);
  
  IOCON->mux_ctl_5 |= IOCON_MUX5_PA1 | IOCON_MUX5_PA0;

  /* ensure Port A bits 0 & 1 are outputs */
  GPIOA->ddr |= (LED_GPIOA_D8 | LED_GPIOA_D11);
  
  while (1)
  {
    GPIOA->dr |= LED_GPIOA_D8; 
    timer_wait_ms(TIMER1, 300, EVB79524_XTAL_IN);
    GPIOA->dr &= ~LED_GPIOA_D8;
    GPIOA->dr |= LED_GPIOA_D11;
    timer_wait_ms(TIMER1, 400, EVB79524_XTAL_IN);
    GPIOA->dr &= ~LED_GPIOA_D11;
  }
}

/***********************************************************************
*
* Function: init_mem
*
* Purpose: Initialize the Static and SDRAM controllers
*
* Parameters: None
*
* Outputs: None
*
* Returns: None.
*
* Notes: Short funtion that calls other routines to configure memory.
*        If more init routines are added (i.e. for CF-CARD) they can be
*        called from here.
*        User should stop watchdog timer, and disable caches and MMU's
*        before calling this function.
*        User should not be executing from SDRAM when this function is
*        invoked.
**********************************************************************/
void init_mem(void)
{
  /* enable External Memory controller */
  EMC->ctrl = EMC_CTL_ENABLE;
  EMC->config = EMC_CFG_SDCCLK_1_1;

  init_ioconfig();
  
  /* init Static RAM */
  init_smc();
  
  /* init Synchronous DRAM */
  init_sdram();
}

/***********************************************************************
*
* Function: init_clocks
*
* Purpose: Initialize CPU, system and pheripheral clocks
*
* Parameters: None
*
* Outputs: None
*
* Returns: None.
*
* Notes: 
**********************************************************************/
void init_clocks(void)
{
  UNS_32 syspll=0;
  
  /* enable APB register write access*/
  RCPC->rcpcctrl = RCPC_PWRDWNSEL_ACTIVE | RCPC_OUTSEL_HCLK |
                  RCPC_CTRL_WRTLOCK_UNLOCKED;
  
  /* set the chip in fast bus mode */
  RCPC->coreclkconfig = RCPC_CCC_FASTBUS;
  /* except SDRAM and DMA disable all other clocks */
  RCPC->ahbclkctrl = RCPC_AHBCLKCTRL_ETHERNET_DISABLE | 
                      RCPC_AHBCLKCTRL_USB_DISABLE |
                      RCPC_AHBCLKCTRL_LCD_DISABLE;
  /* disable all pheripheral clocks */
  RCPC->periphclkctrl0 = RCPC_CLKCTRL0_U0_DISABLE 
                      | RCPC_CLKCTRL0_U1_DISABLE
                      | RCPC_CLKCTRL0_U2_DISABLE
                      | RCPC_CLKCTRL0_RTC_DISABLE;

  RCPC->periphclkctrl1 = RCPC_CLKCTRL1_LCD_DISABLE
                      | RCPC_CLKCTRL1_SSP_DISABLE
                      | RCPC_CLKCTRL1_ADC_DISABLE
                      | RCPC_CLKCTRL1_USB_DISABLE;
  /* set system PLL clock at 101.6064 MHz */
  syspll = RCPC_SPC_FR_100_TO_305 | _BIT(13) |
                       RCPC_SPC_SET_MS(1) | RCPC_SPC_SET_NS(9);

  RCPC->systempllctrl = syspll;

  /* set HCLK at 50.8032 MHz */
  RCPC->hclkprescale = RCPC_PRESCALER_DIV2;
  /* set FCLK at 50.8032 MHz */
  RCPC->cpuclkprescale = RCPC_PRESCALER_DIV2;
  /* set core in ASYNCH clock mode */
  RCPC->coreclkconfig = RCPC_CCC_STDASYNCH; 
}

/***********************************************************************
*
* Function: init_smc
*
* Purpose: Initialize Static Memory Bank Configuration registers 
*
* Parameters: None.
*
* Outputs: None.
*
* Returns: None.
*
* Notes: None.
**********************************************************************/
void init_smc(void)
{
  UNS_64 hclk = 0;
  hclk = RCPC_GET_HCLK(EVB79524_XTAL_IN);
  
  // nCS0 0x40000000 connected to NAND flash
  EMC->static_cfg0 = EMC_STATIC_CFG_MW32;
  EMC->static_waitwen0  = EMC_STATIC_WAIT_WEN(EVB79524_NAND_WAIT_WEN,hclk);
  EMC->static_waitoen0  = EMC_STATIC_WAIT_OEN(EVB79524_NAND_WAIT_OEN, 
                            hclk);
  EMC->static_waitrd0   = EMC_STATIC_WAIT_RD(EVB79524_NAND_WAIT_RD, 
                            hclk);
  EMC->static_waitpage0 = EMC_STATIC_WAIT_PAGE(EVB79524_NAND_WAIT_PAGE, 
                            hclk);
  EMC->static_waitwr0   = EMC_STATIC_WAIT_WR(EVB79524_NAND_WAIT_WR, 
                            hclk);
  EMC->static_waitturn0 = EMC_STATIC_WAIT_TURN(EVB79524_NAND_WAIT_TURN, 
                            hclk);
  
  // nCS1 0x44000000 connected to NOR flash
  EMC->static_cfg1 = EMC_STATIC_CFG_MW16 | EMC_STATIC_CFG_BLS;
  EMC->static_waitwen1  = EMC_STATIC_WAIT_WEN(EVB79524_FLASH_WAIT_WEN,
                            hclk);
  EMC->static_waitoen1  = EMC_STATIC_WAIT_OEN(EVB79524_FLASH_WAIT_OEN,
                            hclk);
  EMC->static_waitrd1   = EMC_STATIC_WAIT_RD(EVB79524_FLASH_WAIT_RD,
                            hclk);
  EMC->static_waitpage1 = EMC_STATIC_WAIT_PAGE(EVB79524_FLASH_WAIT_PAGE,
                            hclk);
  EMC->static_waitwr1   = EMC_STATIC_WAIT_WR(EVB79524_FLASH_WAIT_WR,
                            hclk);
  EMC->static_waitturn1 = EMC_STATIC_WAIT_TURN(EVB79524_FLASH_WAIT_TURN,
                            hclk);
  
  // nCS2 0x48000000 connected to external SRAM
  EMC->static_cfg2 = EMC_STATIC_CFG_MW32;
  EMC->static_waitwen2  = EMC_STATIC_WAIT_WEN(EVB79524_SRAM_WAIT_WEN,
                            hclk);
  EMC->static_waitoen2  = EMC_STATIC_WAIT_OEN(EVB79524_SRAM_WAIT_OEN,
                            hclk);
  EMC->static_waitrd2   = EMC_STATIC_WAIT_RD(EVB79524_SRAM_WAIT_RD,
                            hclk);
  EMC->static_waitpage2 = EMC_STATIC_WAIT_PAGE(EVB79524_SRAM_WAIT_PAGE,
                            hclk);
  EMC->static_waitwr2   = EMC_STATIC_WAIT_WR(EVB79524_SRAM_WAIT_WR,
                            hclk);
  EMC->static_waitturn2 = EMC_STATIC_WAIT_TURN(EVB79524_SRAM_WAIT_TURN,
                            hclk);
  
  // nCS3 0x4C000000 connected to CPLD
  EMC->static_cfg3 = EMC_STATIC_CFG_MW16 | EMC_STATIC_CFG_BLS;
  EMC->static_waitwen3  = EMC_STATIC_WAIT_WEN(EVB79524_CPLD_WAIT_WEN,
                            hclk);
  EMC->static_waitoen3  = EMC_STATIC_WAIT_OEN(EVB79524_CPLD_WAIT_OEN,
                            hclk);
  EMC->static_waitrd3   = EMC_STATIC_WAIT_RD(EVB79524_CPLD_WAIT_RD,
                            hclk);
  EMC->static_waitpage3 = EMC_STATIC_WAIT_PAGE(EVB79524_CPLD_WAIT_PAGE,
                            hclk);
  EMC->static_waitwr3   = EMC_STATIC_WAIT_WR(EVB79524_CPLD_WAIT_WR,
                            hclk);
  EMC->static_waitturn3 = EMC_STATIC_WAIT_TURN(EVB79524_CPLD_WAIT_TURN,
                            hclk);
}

/***********************************************************************
* Function: init_sdram
*
* Purpose: To initialize SDRAM on the EVB79524 hardware
*
* Description: 
*   Two memory banks comprising of two 4Mbit x 16 SDRAM chips
*   64 MBytes total.
*
* nSDCE0 - 32MB at 0x20000000 (SDRAM Bank0 Base)
* nSDCE1 - 32MB at 0x30000000 (SDRAM Bank1 Base)
*
*  ***** Micron Initialization Sequence from their data sheet
*        for the Micron MT48LC16FFG 8Mb x 16 SDRAM chip:
*
*  Initialization
*
*  SDRAMs must be powered up and initialized in a
*  predefined manner. Operational procedures other than
*  those specified may result in undefined operation. Once
*  power is applied to VDD and VDDQ (simultaneously) and
*  the clock is stable (stable clock is defined as a signal
*  cycling within timing constraints specified for the clock
*  pin), the SDRAM requires a 100祍 delay prior to issuing
*  any command other than a COMMAND INHIBIT or NOP.