lh79524_rcpc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

#define RCPC_PRESCALER_DIV30    _SBF(0,15)
/* bit fields for prescaler divider value - divider is 32 */
#define RCPC_PRESCALER_DIV32    _SBF(0,16)
/* bit fields for prescaler divider value - divider is 64 */
#define RCPC_PRESCALER_DIV64    _SBF(0,32)
/* bit fields for prescaler divider value - divider is 128 */
#define RCPC_PRESCALER_DIV128   _SBF(0,64)
/* bit fields for prescaler divider value - divider is 256 */
#define RCPC_PRESCALER_DIV256   _SBF(0,128)
/* bit fields for prescaler divider value - divider is 65534 */
#define RCPC_PRESCALER_DIV65534 (0xFFFF)

#define RCPC_HCLK_PRESCALER()      (RCPC->hclkprescale & _BITMASK(4))
#define RCPC_CPUCLK_PRESCALER()    (RCPC->cpuclkprescale & _BITMASK(4))
#define RCPC_ADCCLK_PRESCALER()    (RCPC->adcclkprescale & _BITMASK(8))
#define RCPC_LCDCLK_PRESCALER()    (RCPC->lcdclkprescale & _BITMASK(8))
#define RCPC_SSPCLK_PRESCALER()    (RCPC->sspclkprescale & _BITMASK(8))

/**********************************************************************
 * periphclkctrl - Peripheral Clock Control Register Bit Fields
 * spareclkctrl - Spare Clock Control Register Bit Fields
 * ahbclkctrl - AHB Clock Control Register Bit Fields
 * Writing a "0" to a bit in these registers enables the
 *  corresponding clock
 *********************************************************************/ 
/* clock disable bit field definition - Uart 0 disable */
#define RCPC_CLKCTRL0_U0_DISABLE         _BIT(0)
/* clock disable bit field definition - Uart 1 disable */
#define RCPC_CLKCTRL0_U1_DISABLE         _BIT(1)
/* clock disable bit field definition - Uart 2 disable */
#define RCPC_CLKCTRL0_U2_DISABLE         _BIT(2)
/* clock disable bit field definition - RTC disable */
#define RCPC_CLKCTRL0_RTC_DISABLE        _BIT(9)

/* clock disable bit field definition - LCD disable */
#define RCPC_CLKCTRL1_LCD_DISABLE        _BIT(0)
/* clock disable bit field definition - SSP disable */
#define RCPC_CLKCTRL1_SSP_DISABLE        _BIT(1)
/* clock disable bit field definition - ADC disable */
#define RCPC_CLKCTRL1_ADC_DISABLE        _BIT(2)
/* clock disable bit field definition - USB disable */
#define RCPC_CLKCTRL1_USB_DISABLE        _BIT(3)

/* clock disable bit field definition - DMA disable */
#define RCPC_AHBCLKCTRL_DMA_DISABLE      _BIT(0)
/* clock disable bit field definition - SDRAMC disable */
#define RCPC_AHBCLKCTRL_SDRAMC_DISABLE   _BIT(1)
/* clock disable bit field definition - ETHERNET disable */
#define RCPC_AHBCLKCTRL_ETHERNET_DISABLE _BIT(2)
/* clock disable bit field definition - USB disable */
#define RCPC_AHBCLKCTRL_USB_DISABLE      _BIT(3)
/* clock disable bit field definition - LCD disable */
#define RCPC_AHBCLKCTRL_LCD_DISABLE      _BIT(4)

/**********************************************************************
 * periphclksel0 - Peripheral Clock Select Register Bit Fields
 * Writing a "0" to U0-U2 in this register enables the
 *  System Clock Oscillator as the clock source
 * Writing a "1" to U0-U2 in this register enables the
 *  HCLK as the clock source
 *********************************************************************/ 
/* clock source select bit field - Uart 0 as external */
#define RCPC_PCLKSEL0_U0_HCLK     _BIT(0) /* U0 Clock Source */ 
/* clock source select bit field - Uart 1 as external */
#define RCPC_PCLKSEL0_U1_HCLK     _BIT(1) /* U1 Clock Source */ 
/* clock source select bit field - Uart 2 as external */
#define RCPC_PCLKSEL0_U2_HCLK     _BIT(2) /* U2 Clock Source */ 

/**********************************************************************
 * periphclksel1 - Peripheral Clock Select Register Bit Fields
 *********************************************************************/ 
/* clock source select bit field - Counter 0 as external 
 * Writing a "0" to RCPC_PCLKSEL1_SSP_SCOC in this register enables 
 * the HCLK as the clock source else Writing a "1" selects System 
 * Clock Oscillator as the clock source
 */
#define RCPC_PCLKSEL1_SSP_SCOC    _BIT(1) /* SSP Clock Source */ 
/* clock source select bit field - Counter 1 as external */
#define RCPC_PCLKSEL1_ADC_SCOC    _BIT(2) /* ADC Clock Source */ 
/* clock source select bit field - Counter 2 as external 
 * Writing a "0" to RCPC_PCLKSEL1_USB_PLL in this register enables 
 * the HCLK as the clock source else Writing a "1" selects USB 
 * PLL clock as the clock source
 */
#define RCPC_PCLKSEL1_USB_PLL     _BIT(3) /* USB Clock Source */ 


/**********************************************************************
 * intconfig - External Interrupt Configuration Register Bit Fields
 *********************************************************************/ 
/* macro definition for Intconfig register */
#define RCPC_INTCONFIG(f,v)     _SBF((f),(v))
/* RCPC_INTCONFIG arguments for 'f' parameter */ 
/* bit field - RCPC intconfig select INT 0 */
#define RCPC_INT0       0
/* bit field - RCPC intconfig select INT 1 */
#define RCPC_INT1       2
/* bit field - RCPC intconfig select INT 2 */
#define RCPC_INT2       4
/* bit field - RCPC intconfig select INT 3 */
#define RCPC_INT3       6
/* bit field - RCPC intconfig select INT 4 */
#define RCPC_INT4       8
/* bit field - RCPC intconfig select INT 5 */
#define RCPC_INT5       10
/* bit field - RCPC intconfig select INT 6 */
#define RCPC_INT6       12
/* bit field - RCPC intconfig select INT 7 */
#define RCPC_INT7       14
/* RCPC_INTCONFIG arguments for 'v' parameter */ 
/* bit fields for external INT trigger level - low level */
#define RCPC_INT_LLT    0       /* Low Level Trigger */ 
/* bit fields for external INT trigger level - high level */
#define RCPC_INT_HLT    1       /* High Level Trigger */ 
/* bit fields for external INT trigger level - falling edge */
#define RCPC_INT_FET    2       /* Falling Edge Trigger */ 
/* bit fields for external INT trigger level - rising edge */
#define RCPC_INT_RET    3       /* Rising Edge Trigger */ 

/**********************************************************************
 * intclear - External Interrupt Clear Register Bit Fields
 *********************************************************************/ 
/* macro for intclear register bit fields */
#define RCPC_INTCLEAR(n)    _BIT(n) /* Clear Edge Interrupt 'n' */ 

/**********************************************************************
 * coreclkconfig - Core Clock Configuration Register Bit Fields
 *********************************************************************/ 
/* bit fields for coreclkconfig register - standard mode, async */
#define RCPC_CCC_STDASYNCH      0 /* Standard Mode, Asynch operation */
/* bit fields for coreclkconfig register - fast bus mode */
#define RCPC_CCC_FASTBUS        1 /* Fast Bus Extension Mode */
/* bit fields for coreclkconfig register - standard mode, sync */
#define RCPC_CCC_STDSYNCH       2 /* Standard Mode, Synch operation */

/**********************************************************************
 * SystemPLLCtrl - System PLL Control Register Bit Fields
 *********************************************************************/ 
#define RCPC_SPC_FR_100_TO_305      _BIT(12)
#define RCPC_SPC_MS(x)              ((x >> 6) & _BITMASK(6))
#define RCPC_SPC_NS(x)              (x & _BITMASK(6))
#define RCPC_SPC_SET_MS(x)          ((x & _BITMASK(6)) << 6)
#define RCPC_SPC_SET_NS(x)          (x & _BITMASK(6))


/* Macro pointing to RCPC registers */
#define RCPC    ((RCPC_REGS_T *)(RCPC_BASE))

/**********************************************************************
 *  Macros to compute system clocks based on XTALIN
 *********************************************************************/
#define RCPC_GET_SYSPLL(X)      \
    ((UNS_64)((X) * RCPC_SPC_NS(RCPC->systempllctrl))/\
    RCPC_SPC_MS(RCPC->systempllctrl))

#define RCPC_GET_HCLK(X)        \
    (RCPC_GET_SYSPLL(X)/(1 << RCPC_HCLK_PRESCALER()))
 
#define RCPC_GET_CPUCLK(X)      \
    (RCPC_GET_SYSPLL(X)/(1 << RCPC_CPUCLK_PRESCALER()))
 

#endif /* LH79524_RCPC_H */