lh79524_emc.h

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

#define EMC_SDRAMC_CTL_CS             _BIT(1)
#define EMC_SDRAMC_CTL_SR             _BIT(2)
#define EMC_SDRAMC_CTL_MCC            _BIT(5)
#define EMC_SDRAMC_CTL_NORMAL_CMD     _SBF(7,0)
#define EMC_SDRAMC_CTL_MODE_CMD       _SBF(7,1)
#define EMC_SDRAMC_CTL_PALL_CMD       _SBF(7,2)
#define EMC_SDRAMC_CTL_NOP_CMD        _SBF(7,3)
#define EMC_SDRAMC_CTL_DP             _BIT(8)

#define EMC_SDRAMC_CFG_SDRAM_MD       _SBF(3,0)
#define EMC_SDRAMC_CFG_LOW_PWR_MD     _SBF(3,1)
#define EMC_SDRAMC_CFG_SYNC_FLASH     _SBF(3,2)
#define EMC_SDRAMC_CFG_BUF_EN         _BIT(19)
#define EMC_SDRAMC_CFG_WP             _BIT(20)

/*16-bit external bus high-performance address mapping */
/*16Mb (2Mx8), 2 banks, row length = 11, column length = 9*/
#define SDRAMC_16HP_2Mx8_2B_R11_C9    (_SBF(7,0x00))
/*16Mb (1Mx16), 2 banks, row length = 11, column length = 8*/
#define SDRAMC_16HP_1Mx16_2B_R11_C8   (_SBF(7,0x01))
/*64Mb (8Mx8), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_16HP_8Mx8_4B_R12_C9    (_SBF(7,0x04))
/*64Mb (4Mx16), 4 banks, row length = 12, column length = 8*/
#define SDRAMC_16HP_4Mx16_4B_R12_C8   (_SBF(7,0x05))
/*128Mb (16Mx8), 4 banks, row length = 12, column length = 10*/
#define SDRAMC_16HP_16Mx8_4B_R12_C10  (_SBF(7,0x08))
/*128Mb (8Mx16), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_16HP_8Mx16_4B_R12_C9   (_SBF(7,0x09))
/*256Mb (32Mx8), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_16HP_32Mx8_4B_R13_C10  (_SBF(7,0x0C))
/*256Mb (16Mx16), 4 banks, row length = 13, column length = 9*/
#define SDRAMC_16HP_16Mx16_4B_R13_C9  (_SBF(7,0x0D))
/*512Mb (64Mx8), 4 banks, row length = 13, column length = 11*/
#define SDRAMC_16HP_64Mx8_4B_R13_C11  (_SBF(7,0x10))
/*512Mb (32Mx16), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_16HP_32Mx16_4B_R13_C10 (_SBF(7,0x11))

/*16-bit external bus low power SDRAM address mapping */
/*16Mb (2Mx8), 2 banks, row length = 11, column length = 9*/
#define SDRAMC_16LP_2Mx8_2B_R11_C9    (_SBF(7,0x20))
/*16Mb (1Mx16), 2 banks, row length = 11, column length = 8*/
#define SDRAMC_16LP_1Mx16_2B_R11_C8   (_SBF(7,0x21))
/*64Mb (8Mx8), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_16LP_8Mx8_4B_R12_C9    (_SBF(7,0x24))
/*64Mb (4Mx16), 4 banks, row length = 12, column length = 8*/
#define SDRAMC_16LP_4Mx16_4B_R12_C8   (_SBF(7,0x25))
/*128Mb (16Mx8), 4 banks, row length = 12, column length = 10*/
#define SDRAMC_16LP_16Mx8_4B_R12_C10  (_SBF(7,0x28))
/*128Mb (8Mx16), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_16LP_8Mx16_4B_R12_C9   (_SBF(7,0x29))
/*256Mb (32Mx8), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_16LP_32Mx8_4B_R13_C10  (_SBF(7,0x2C))
/*256Mb (16Mx16), 4 banks, row length = 13, column length = 9*/
#define SDRAMC_16LP_16Mx16_4B_R13_C9  (_SBF(7,0x2D))
/*512Mb (64Mx8), 4 banks, row length = 13, column length = 11*/
#define SDRAMC_16LP_64Mx8_4B_R13_C11  (_SBF(7,0x30))
/*512Mb (32Mx16), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_16LP_32Mx16_4B_R13_C10 (_SBF(7,0x31))

/*32-bit external bus high-performance address mapping */
/*16Mb (2Mx8), 2 banks, row length = 11, column length = 9*/
#define SDRAMC_32HP_2Mx8_2B_R11_C9    (_SBF(7,0x00) | _BIT(14))
/*16Mb (1Mx16), 2 banks, row length = 11, column length = 8*/
#define SDRAMC_32HP_1Mx16_2B_R11_C8   (_SBF(7,0x01) | _BIT(14))
/*64Mb (8Mx8), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_32HP_8Mx8_4B_R12_C9    (_SBF(7,0x04) | _BIT(14))
/*64Mb (4Mx16), 4 banks, row length = 12, column length = 8*/
#define SDRAMC_32HP_4Mx16_4B_R12_C8   (_SBF(7,0x05) | _BIT(14))
/*128Mb (16Mx8), 4 banks, row length = 12, column length = 10*/
#define SDRAMC_32HP_16Mx8_4B_R12_C10  (_SBF(7,0x08) | _BIT(14))
/*128Mb (8Mx16), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_32HP_8Mx16_4B_R12_C9   (_SBF(7,0x09) | _BIT(14))
/*256Mb (32Mx8), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_32HP_32Mx8_4B_R13_C10  (_SBF(7,0x0C) | _BIT(14))
/*256Mb (16Mx16), 4 banks, row length = 13, column length = 9*/
#define SDRAMC_32HP_16Mx16_4B_R13_C9  (_SBF(7,0x0D) | _BIT(14))
/*512Mb (64Mx8), 4 banks, row length = 13, column length = 11*/
#define SDRAMC_32HP_64Mx8_4B_R13_C11  (_SBF(7,0x10) | _BIT(14))
/*512Mb (32Mx16), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_32HP_32Mx16_4B_R13_C10 (_SBF(7,0x11) | _BIT(14))

/*32-bit external bus low power SDRAM address mapping */
/*16Mb (2Mx8), 2 banks, row length = 11, column length = 9*/
#define SDRAMC_32LP_2Mx8_2B_R11_C9    (_SBF(7,0x20) | _BIT(14))
/*16Mb (1Mx16), 2 banks, row length = 11, column length = 8*/
#define SDRAMC_32LP_1Mx16_2B_R11_C8   (_SBF(7,0x21) | _BIT(14))
/*64Mb (8Mx8), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_32LP_8Mx8_4B_R12_C9    (_SBF(7,0x24) | _BIT(14))
/*64Mb (4Mx16), 4 banks, row length = 12, column length = 8*/
#define SDRAMC_32LP_4Mx16_4B_R12_C8   (_SBF(7,0x25) | _BIT(14))
/*128Mb (16Mx8), 4 banks, row length = 12, column length = 10*/
#define SDRAMC_32LP_16Mx8_4B_R12_C10  (_SBF(7,0x28) | _BIT(14))
/*128Mb (8Mx16), 4 banks, row length = 12, column length = 9*/
#define SDRAMC_32LP_8Mx16_4B_R12_C9   (_SBF(7,0x29) | _BIT(14))
/*256Mb (32Mx8), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_32LP_32Mx8_4B_R13_C10  (_SBF(7,0x2C) | _BIT(14))
/*256Mb (16Mx16), 4 banks, row length = 13, column length = 9*/
#define SDRAMC_32LP_16Mx16_4B_R13_C9  (_SBF(7,0x2D) | _BIT(14))
/*512Mb (64Mx8), 4 banks, row length = 13, column length = 11*/
#define SDRAMC_32LP_64Mx8_4B_R13_C11  (_SBF(7,0x30) | _BIT(14))
/*512Mb (32Mx16), 4 banks, row length = 13, column length = 10*/
#define SDRAMC_32LP_32Mx16_4B_R13_C10 (_SBF(7,0x31) | _BIT(14))

#define EMC_SDRAMC_RDCFG_CLKOUTDELAY_STG       _SBF(0,0)
#define EMC_SDRAMC_RDCFG_CMDDELAY_STG          _SBF(0,1) 
#define EMC_SDRAMC_RDCFG_CMDDELAY_P1_STG       _SBF(0,2)
#define EMC_SDRAMC_RDCFG_CMDDELAY__P2_STG      _SBF(0,3)

#define EMC_SDRAMC_RASCAS_CAS0        _SBF(8,0)
#define EMC_SDRAMC_RASCAS_CAS1        _SBF(8,1)
#define EMC_SDRAMC_RASCAS_CAS2        _SBF(8,2)
#define EMC_SDRAMC_RASCAS_CAS3        _SBF(8,3)
#define EMC_SDRAMC_RASCAS_RAS0        _SBF(0,0)
#define EMC_SDRAMC_RASCAS_RAS1        _SBF(0,1)
#define EMC_SDRAMC_RASCAS_RAS2        _SBF(0,2)
#define EMC_SDRAMC_RASCAS_RAS3        _SBF(0,3)

#define EMC_CLOCK(hclk)               \
    (hclk/(((EMC->config & _BIT(8))>>8)+1))

#define EMC_SDRAMC_REFRESH(trf,hclk)  \
    (((UNS_64)(trf * hclk)/16000000000) & _BITMASK(11))

#define EMC_SDRAMC_TRP(trp,hclk)      \
    (((UNS_64)(trp * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TRAS(tras,hclk)    \
    (((UNS_64)(tras * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TSREX(tsrex,hclk)  \
    (((UNS_64)(tsrex * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TARP(tarp,hclk)    \
    (((UNS_64)(tarp * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TDAL(tdal,hclk)    \
    (((UNS_64)(tdal * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TWR(twr,hclk)      \
    (((UNS_64)(twr * EMC_CLOCK(hclk))/1000000000) & _BITMASK(4))
#define EMC_SDRAMC_TRC(trc,hclk)      \
    (((UNS_64)(trc * EMC_CLOCK(hclk))/1000000000) & _BITMASK(5))
#define EMC_SDRAMC_TRFC(trfc,hclk)    \
    (((UNS_64)(trfc * EMC_CLOCK(hclk))/1000000000) & _BITMASK(5))
#define EMC_SDRAMC_TXSR(txsr,hclk)    \
    (((UNS_64)(txsr * EMC_CLOCK(hclk))/1000000000) & _BITMASK(5))
#define EMC_SDRAMC_TRRD(trrd,hclk)    \
    (((UNS_64)(trrd * EMC_CLOCK(hclk))/1000000000) & _BITMASK(5))
#define EMC_SDRAMC_TMRD(tmrd,hclk)    \
    (((UNS_64)(tmrd * EMC_CLOCK(hclk))/1000000000) & _BITMASK(5))


/*Static Memory Controler defines*/

#define EMC_STATIC_CFG_MW8      _SBF(0,0)  /* Memory width 8 bits */
#define EMC_STATIC_CFG_MW16     _SBF(0,1)  /* Memory width 16 bits */
#define EMC_STATIC_CFG_MW32     _SBF(0,2)  /* Memory width 16 bits */

#define EMC_STATIC_CFG_PM       _SBF(3,1)
#define EMC_STATIC_CFG_PC       _SBF(6,1)
#define EMC_STATIC_CFG_BLS      _SBF(7,1)
#define EMC_STATIC_CFG_EW       _SBF(8,1)
#define EMC_STATIC_CFG_B        _SBF(19,1)
#define EMC_STATIC_CFG_P        _SBF(20,1)

#define EMC_STATIC_EXWAIT(twait,hclk)   \
    (((UNS_64)(twait * hclk)/16000000000) & _BITMASK(10))

#define EMC_STATIC_WAIT_WEN(twen,hclk)  \
    (((UNS_64)(twen * hclk)/1000000000) & _BITMASK(4))

#define EMC_STATIC_WAIT_OEN(toen,hclk)  \
    (((UNS_64)(toen * hclk)/1000000000) & _BITMASK(4))

#define EMC_STATIC_WAIT_RD(trd,hclk)    \
    (((UNS_64)(trd * hclk)/1000000000) & _BITMASK(5))

#define EMC_STATIC_WAIT_PAGE(tpg,hclk)  \
    (((UNS_64)(tpg * hclk)/1000000000) & _BITMASK(5))

#define EMC_STATIC_WAIT_WR(twr,hclk)    \
    (((UNS_64)(twr * hclk)/1000000000) & _BITMASK(5))

#define EMC_STATIC_WAIT_TURN(trn,hclk)  \
    (((UNS_64)(trn * hclk)/1000000000) & _BITMASK(4))


/* Macro pointing to vectored interrupt controller 1 registers */
#define EMC ((EMC_REGS_T *)(EMC_REGS_BASE))

#endif /* LH79524_EMC_H */