📄 lh79524_sdk_audio_driver.c
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reg_value |= (1<<1);
audio_spi_configure(REG_DIGITAL_PATH, reg_value);
reg_digital_path_default = reg_value;
}
else if(arg == DE_EM_44KHZ)
{
/* Digital audio de-emphasis is 44.1 khz */
reg_value = reg_digital_path_default & (~(_BIT(2)|_BIT(1)));
reg_value |= (2<<1);
audio_spi_configure(REG_DIGITAL_PATH, reg_value);
reg_digital_path_default = reg_value;
}
else if(arg == DE_EM_48KHZ)
{
/* Digital audio de-emphasis is 48 khz */
reg_value = reg_digital_path_default & (~(_BIT(2)|_BIT(1)));
reg_value |= (3<<1);
audio_spi_configure(REG_DIGITAL_PATH, reg_value);
reg_digital_path_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case POWER_ON:
if(arg == 1)
{
/* Turn on power */
reg_value = reg_power_down_default & (~_BIT(7));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off power */
reg_value = reg_power_down_default | _BIT(7);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case CLOCK_ON:
if(arg == 1)
{
/* Turn on clock */
reg_value = reg_power_down_default & (~_BIT(6));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off clock */
reg_value = reg_power_down_default | _BIT(6);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case OSCILLATOR_ON:
if(arg == 1)
{
/* Turn on oscillator */
reg_value = reg_power_down_default & (~_BIT(5));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off oscillator */
reg_value = reg_power_down_default | _BIT(5);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case OUTPUTS_ON:
if(arg == 1)
{
/* Turn on output */
reg_value = reg_power_down_default & (~_BIT(4));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off output */
reg_value = reg_power_down_default | _BIT(4);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DAC_ON:
if(arg == 1)
{
/* Turn on DAC */
reg_value = reg_power_down_default & (~_BIT(3));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off DAC */
reg_value = reg_power_down_default | _BIT(3);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case LINE_INPUT_ON:
if(arg == 1)
{
/* Turn on Line input */
reg_value = reg_power_down_default & (~_BIT(0));
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else if(arg == 0)
{
/* Turn off Line input */
reg_value = reg_power_down_default | _BIT(0);
audio_spi_configure(REG_POWER_DOWN, reg_value);
reg_power_down_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_MASTER_MODE:
if(arg == 1)
{
/* Set as master mode */
reg_value = reg_digital_format_default | _BIT(6);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 0)
{
/* Set as slave mode */
reg_value = reg_digital_format_default & (~_BIT(6));
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_DAC_LEFT_RIGHT_SWAP:
if(arg == 1)
{
/* Enable DAC left/right swap */
reg_value = reg_digital_format_default | _BIT(5);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 0)
{
/* Disable DAC left/right swap */
reg_value = reg_digital_format_default & (~_BIT(5));
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_DAC_LEFT_RIGHT_PHASE:
if(arg == 1)
{
/* DAC left/right phase - Right channel on,
LRCIN low */
reg_value = reg_digital_format_default | _BIT(4);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 0)
{
/* DAC left/right phase - Right channel on,
LRCIN high */
reg_value = reg_digital_format_default & (~_BIT(4));
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_INPUT_BIT_LENGTH:
if(arg == 16)
{
/* Input bit length is 16 bit */
reg_value = reg_digital_format_default & (~(_BIT(3)|_BIT(2)));
reg_value |= (0x0<<2);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 20)
{
/* Input bit length is 20 bit */
reg_value = reg_digital_format_default & (~(_BIT(3)|_BIT(2)));
reg_value |= (0x1<<2);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 24)
{
/* Input bit length is 24 bit */
reg_value = reg_digital_format_default & (~(_BIT(3)|_BIT(2)));
reg_value |= (0x2<<2);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == 32)
{
/* Input bit length is 32 bit */
reg_value = reg_digital_format_default & (~(_BIT(3)|_BIT(2)));
reg_value |= (0x3<<2);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_DATA_FORMAT:
if(arg == FORMAT_MSB_RIGHT)
{
/* Data format is MSB first, right aligned */
reg_value = reg_digital_format_default & (~(_BIT(0)|_BIT(1)));
reg_value |= (0);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == FORMAT_MSB_LEFT)
{
/* Data format is MSB first, left aligned */
reg_value = reg_digital_format_default & (~(_BIT(0)|_BIT(1)));
reg_value |= (1);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == FORMAT_I2S)
{
/* Data format is I2S format, MSB first, left - 1 aligned */
reg_value = reg_digital_format_default & (~(_BIT(0)|_BIT(1)));
reg_value |= (2);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else if(arg == FORMAT_DSP)
{
/* Data format is DSP format, frame sync followed
by two data words */
reg_value = reg_digital_format_default & (~(_BIT(0)|_BIT(1)));
reg_value |= (3);
audio_spi_configure(REG_DIGITAL_FORMAT, reg_value);
reg_digital_format_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case CLOCK_OUTPUT_DIVIDER:
if(arg == 1)
{
/* Sample rate clock output divider is MCLK/2 */
reg_value = reg_sample_rate_default | _BIT(7);
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else if(arg == 0)
{
/* Sample rate clock output divider is MCLK */
reg_value = reg_sample_rate_default & (~_BIT(7));
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case CLOCK_INPUT_DIVIDER:
if(arg == 1)
{
/* Sample rate clock input divider is MCLK/2 */
reg_value = reg_sample_rate_default | _BIT(6);
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else if(arg == 0)
{
/* Sample rate clock input divider is MCLK */
reg_value = reg_sample_rate_default & (~_BIT(6));
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case SAMPLE_RATE_VALUE:
/* Set SR3, SR2, SR1 and SR0 value - arg
represents SR3 to SR0 */
if((arg <= 0xf) && (arg >= 0))
{
/* Set SR3 to SR0 value as arg */
reg_value = reg_sample_rate_default &
(~(_BIT(5)|_BIT(4)|_BIT(3)|_BIT(2)));
reg_value |= (arg << 2);
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case BASE_OVERSAMPLING_RATE:
if(arg == 1)
{
/* Base oversampling rate - USB mode, 272fs
Normal mode, 384fs */
reg_value = reg_sample_rate_default | _BIT(1);
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else if(arg == 0)
{
/* Base oversampling rate - USB mode, 250fs
Normal mode, 256fs */
reg_value = reg_sample_rate_default & (~_BIT(1));
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case USB_NORMAL_MODE:
if(arg == 1)
{
/* Clock mode select - USB mode */
reg_value = reg_sample_rate_default | _BIT(0);
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else if(arg == 0)
{
/* Clock mode select - Normal mode */
reg_value = reg_sample_rate_default & (~_BIT(0));
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
reg_sample_rate_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case DIGITAL_ACTIVATE_INTERFACE:
if(arg == 1)
{
/* Digital interface active */
reg_value = reg_digital_activation_default | _BIT(0);
audio_spi_configure(REG_DIGITAL_ACTIVATION, reg_value);
reg_digital_activation_default = reg_value;
}
else if(arg == 0)
{
/* Digital interface inactive */
reg_value = reg_digital_activation_default & (~_BIT(0));
audio_spi_configure(REG_DIGITAL_ACTIVATION, reg_value);
reg_digital_activation_default = reg_value;
}
else
{
result = _ERROR;
}
break;
case RESET_CHIP:
if(arg == 1)
{
/* RESET the chip */
reg_value = reg_reset_default;
audio_spi_configure(REG_RESET, reg_value);
reg_reset_default = reg_value;
}
else
{
result = _ERROR;
}
break;
/* SDK79520 board uses 5.6448Mhz, only below sample rate
available in normal mode */
/*
case SDK79520_SAMPLE_RATE_CONTROL:
if(arg == R_44P1_KHZ)
{
reg_value = 0x3f;
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
}
else if(arg == R_22P05_KHZ)
{
reg_value = 0x20;
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
}
else if(arg == R_11P025_KHZ)
{
reg_value = 0x60;
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
}
else if(arg == R_4P01_KHZ)
{
reg_value = 0x2c;
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
}
else if(arg == R_2_KHZ)
{
reg_value = 0x68;
audio_spi_configure(REG_SAMPLE_RATE, reg_value);
}
else
{
result = _ERROR;
}
break;
*/
default:
result = _ERROR;
break;
}
return result;
}
/**********************************************************************
*
* Function: audio_spi_configure
*
* Purpose:
* Use SPI line controlled by CPLD on SDK79520 board
* to configure TI TLV320DAC23 audio chip
*
* Processing:
*
* Parameters:
* reg_addr: address for the control registers
* value: value to be written to the specific register
* arg = 0 for no. Detail to see the comments in the code
*
* Outputs:
* None
*
* Returns:
* None
*
* Notes:
* function coded as per Logic PD spec.
*
**********************************************************************/
#define COD_ADDR *(volatile UNS_16 *)(0x4c500000)
#define COD_nCS (_BIT(5))
#define COD_CLK (_BIT(2))
#define COD_DI (_BIT(1))
void audio_spi_configure(INT_32 reg_addr, INT_32 value)
{
int spi_data, i;
spi_data = (value & 0x1ff) | (reg_addr << 9);
// set nCS clk and di low
COD_ADDR = 0;
for(i=0;i<16;i++)
{
// set clk low
COD_ADDR &=~(COD_CLK);
// set sdi according to the data
if((spi_data & _BIT(15-i)) != 0)
{
COD_ADDR |= COD_DI;
}
else
{
COD_ADDR &= ~COD_DI;
}
// set clk high to latch the data
COD_ADDR |= COD_CLK;
}
// set nCS, clk and di high
COD_ADDR = COD_nCS;
}
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