📄 entry.s
字号:
B150
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B150
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x4800,0000- Controled by CS2
; to virtual memory 0x4800,0000-
; 64M bytes of addressing, 64 entry in the MMU table
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LDR r1,=MMU_TRANS_TABLE ; MMU table start address
LDR r2,=0x48000000 ; physical memory
LDR r3,=0x48000000 ; virtual memory
MOV r0,#64 ; number of MBytes
MOV r3,r3,lsr #20 ; r3>>20
MOV r3,r3,lsl #2 ; r3<<2
ADD r1,r1,r3 ; Get correct entry in
; MMU translation table
ADD r2,r2,#CACHE_WB_OFF ; Cache and WB control
ADD r2,r2,#SECTION_DOMAIN
B160
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B160
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x4C00,0000- Controled by CS3
; to virtual memory 0x4C00,0000-
; 64M bytes of addressing, 64 entry in the MMU table
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LDR r1,=MMU_TRANS_TABLE ; MMU table start address
LDR r2,=0x4C000000 ; physical memory
LDR r3,=0x4C000000 ; virtual memory
MOV r0,#64 ; number of MBytes
MOV r3,r3,lsr #20 ; r3>>20
MOV r3,r3,lsl #2 ; r3<<2
ADD r1,r1,r3 ; Get correct entry in
; MMU translation table
ADD r2,r2,#CACHE_WB_OFF ; Cache and WB control
ADD r2,r2,#SECTION_DOMAIN
B170
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B170
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x5000,0000- Controled by CS4
; to virtual memory 0x5000,0000-
; 64M bytes of addressing, 64 entry in the MMU table
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LDR r1,=MMU_TRANS_TABLE ; MMU table start address
LDR r2,=0x50000000 ; physical memory
LDR r3,=0x50000000 ; virtual memory
MOV r0,#64 ; number of MBytes
MOV r3,r3,lsr #20 ; r3>>20
MOV r3,r3,lsl #2 ; r3<<2
ADD r1,r1,r3 ; Get correct entry in
; MMU translation table
ADD r2,r2,#CACHE_WB_OFF ; Cache and WB control
ADD r2,r2,#SECTION_DOMAIN
B180
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B180
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x5400,0000- Controled by CS5
; to virtual memory 0x5400,0000-
; 64M bytes of addressing, 64 entry in the MMU table
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LDR r1,=MMU_TRANS_TABLE ; MMU table start address
LDR r2,=0x54000000 ; physical memory
LDR r3,=0x54000000 ; virtual memory
MOV r0,#64 ; number of MBytes
MOV r3,r3,lsr #20 ; r3>>20
MOV r3,r3,lsl #2 ; r3<<2
ADD r1,r1,r3 ; Get correct entry in
; MMU translation table
ADD r2,r2,#CACHE_WB_OFF ; Cache and WB control
ADD r2,r2,#SECTION_DOMAIN
B190
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B190
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x5800,0000- Controled by CS6
; to virtual memory 0x5800,0000-
; 64M bytes of addressing, 64 entry in the MMU table
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LDR r1,=MMU_TRANS_TABLE ; MMU table start address
LDR r2,=0x58000000 ; physical memory
LDR r3,=0x58000000 ; virtual memory
MOV r0,#64 ; number of MBytes
MOV r3,r3,lsr #20 ; r3>>20
MOV r3,r3,lsl #2 ; r3<<2
ADD r1,r1,r3 ; Get correct entry in
; MMU translation table
ADD r2,r2,#CACHE_WB_OFF ; Cache and WB control
ADD r2,r2,#SECTION_DOMAIN
B200
STR r2,[r1],#4 ; Set table value
ADD r2,r2,#0x100000 ; Add 1MBytes addr
SUBS r0,r0,#1 ; Reduce number of MBytes
BGT B200
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; point translation table base at the translation table
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Set up the Domain Access Control as all Manager
; Make all domains all open
MOV r1,#0xFFFFFFFF
MCR p15, 0, r1, c3, c0, 0
; Flush Unified TLB
MOV r1,#0x0
MCR p15, 0, r1, c8, c7, 0
; Invalidate ID Cache
MCR p15, 0, r1, c7, c7, 0
; Set up TTB
LDR r0,=MMU_TRANS_TABLE
MCR p15, 0, r0, c2, c0, 0
; Set up to jump to virtual location
LDR r3,= init_stacks
; Enable the MMU
; MOV r1, #0x71
LDR r1, =MMU_ENABLE ;enable cache, enable write buffer
MCR p15, 0, r1, c1, c0, 0
NOP ; These NOP are in the pipeline and do nothing
NOP ; as they are executed.
NOP
NOP
NOP
NOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Jump to the virtual address which is in R3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MOV pc, r3 ; Jump to the virtual address which is in R3.
NOP ; These NOP are in the pipeline and do nothing
NOP ; as they are executed.
NOP
NOP
NOP
NOP
init_stacks
; --- Initialize stack pointer registers
; Enter IRQ mode and set up the IRQ stack pointer
MOV r0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =IRQ_Stack
; Enter FIQ mode and set up the FIQ stack pointer
MOV r0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =FIQ_Stack
; Enter ABT mode and set up the ABT stack pointer
MOV r0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =ABT_Stack
; Enter IRQ mode and set up the IRQ stack pointer
MOV r0, #Mode_UNDEF:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =UNDEF_Stack
; Set up the SVC stack pointer last and return to SVC mode
MOV r0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
MSR cpsr_c, r0
LDR sp, =SVC_Stack
; Zero Initialize memory
MOV r3, #0
LDR r0, =|Image$$ER_ZI$$ZI$$Length|
LDR r2, =|Image$$ER_ZI$$Base|
CMP r0, #0
BEQ %F91
90
STR r3, [r2], #4
SUBS r0, r0, #4
BGT %B90
91
;initialize the heap
IMPORT _init_alloc
IMPORT ||Image$$ER_ZI$$ZI$$Limit||
LDR r0,=||Image$$ER_ZI$$ZI$$Limit||
LDR r1,=USR_Stack-0x10000 ;64k user stack
BL _init_alloc
; Turn on MMU
LDR r1,=MMU_ENABLE ;enable cache, enable write buffer
MCR p15, 0, r1, c1, c0, 0
; --- Now we enter the main C application code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IMPORT SharpMain
; DO THE REST OF THINGS IN C UNLESS IT IS NOT POSSIBLE
BL SharpMain ; in C_main.c
mov pc, #0x0 ;if there is return from main, reset
; If above subroutine ever returns, just sit in an endless loop
here B here
EXPORT __main ; defined to ensure C runtime lib is not linked in
__main ; defined to ensure C runtime lib is not linked in
EXPORT main ; defined to ensure C runtime lib is not linked in
main ; defined to ensure C runtime lib is not linked in
mov pc, #0x0 ;if there is return from main, reset
END
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