entry.s

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

;***********************************************************************
; * $Workfile:    $
; * $Revision: 1.2 $
; * $Author: quendez $
; * $Date: 2004/10/15 10:04:18 $
; *
; * Project:  LH79524
; *
;
; * $Log: entry.s,v $
; *
; 
; *  COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
; *                         CAMAS, WA
;**********************************************************************/
;
; This code performs all the initialization required before
; branching to the main C application code.  It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code.
;

                AREA    |!LH79524_RUNTIME|, CODE, READONLY

; Some standard definitions...

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F            ; only available on ARM Arch. v4

I_Bit           EQU     0x80
F_Bit           EQU     0x40

; Locations of our memory system
MEMORY_Limit    EQU     0x22000000              
; = Total 32M SDRAM on LPD board, end of memory is 0x01ff,ffff
; memory 0x20000000 to 0x21ffffff is mirror of memory
; 0x0 to 0x01ffffff
Stack_Limit     EQU     MEMORY_Limit - 0x10 
SVC_Stack       EQU     Stack_Limit             ; = 0x400 bytes
ABT_Stack       EQU     SVC_Stack - 0x400       ; = 0x200 bytes
UNDEF_Stack     EQU     ABT_Stack - 0x200       ; = 0x200 bytes
IRQ_Stack       EQU     UNDEF_Stack - 0x200     ; = 0x200 bytes
FIQ_Stack       EQU     IRQ_Stack - 0x200       ; = 0x200
USR_Stack       EQU     FIQ_Stack - 0x200       ; = XXX bytes          

; MMU control related definition
MMU_TRANS_TABLE	EQU		0x60004000		;MMU translation table in 
										;internal SRAM 16KB
										;Protected, user not to use
SECTION_DOMAIN	EQU		0xC00			;Fixed domain access										
CACHE_WB_ON		EQU		0x1E			;Translation 1M table cache
										;write buffer on entry
CACHE_WB_OFF	EQU		0x12			;Translation 1M table cache
										;write buffer off entry
MMU_ENABLE		EQU		0x27F			;MMU enable,cache wb on, 
										;align, rom protect


        IMPORT  |Image$$ER_RO$$Base|
        IMPORT  |Image$$ER_RO$$Length|
        IMPORT  |Load$$ER_RO$$Base|
        IMPORT  |Image$$ER_RW$$Base|
        IMPORT  |Image$$ER_RW$$Length|
        IMPORT  |Load$$ER_RW$$Base|
        IMPORT  |Image$$ER_ZI$$Base|
        IMPORT  |Image$$ER_ZI$$Length|
        IMPORT  |Image$$ER_ZI$$ZI$$Length|


        EXPORT  _runtime
        ENTRY
_runtime
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;	DO ALL NECESSARY HARDWARE INITIALIZATION HERE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;	Logic board already did so



;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;	Disable MMU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	    MOV 	r1, #0x70		;Disable MMU
    	MCR		p15, 0, r1, c1, c0, 0

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Set up the MMU page tables 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Clear the page table memory 
    	MOV	    r3,#0
	    MOV 	r0,#16384          		; 16K of RAM
    	LDR 	r2,=MMU_TRANS_TABLE    	; Translation table start addr
B92
    	STR		r3,[r2], #4				; Clear translation table
	    SUBS	r0,r0, #4
    	BGT		B92

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical SDRAM at 0x2000,0000-0x21FF,FFFF 
; to virtual memory 0x0000,0000-0x01FF,FFFF
; 32M bytes of addressing, 32 entry in the MMU table	
; cache off, write buffer off
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0x20000000			; physical memory
        LDR		r3,=0					; virtual memory
    	MOV 	r0,#32             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_OFF		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN
B100
	    STR		r2,[r1],#4				; Set table value
        ADD     r2,r2,#0x100000			; Add 1MBytes addr
    	SUBS	r0,r0,#1				; Reduce number of MBytes
	    BGT		B100

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical SDRAM at 0x2000,0000-0x21FF,FFFF 
; to virtual memory 0x2000,0000-0x21FF,FFFF
; 32M bytes of addressing, 32 entry in the MMU table	
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0x20000000			; physical memory
        LDR		r3,=0x20000000			; virtual memory
    	MOV 	r0,#32             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_ON		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN
B110
	    STR		r2,[r1],#4				; Set table value
        ADD     r2,r2,#0x100000			; Add 1MBytes addr
    	SUBS	r0,r0,#1				; Reduce number of MBytes
	    BGT		B110

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map internal peripheral at 0xFFF0,0000-
; to virtual memory 0xFFF0,0000-
; 1M bytes of addressing, 1 entry in the MMU table	
; cache off, write buffer off
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0xFFF00000			; physical memory
        LDR		r3,=0xFFF00000			; virtual memory
    	MOV 	r0,#1             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_OFF		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN
B120
	    STR		r2,[r1],#4				; Set table value
        ADD     r2,r2,#0x100000			; Add 1MBytes addr
    	SUBS	r0,r0,#1				; Reduce number of MBytes
	    BGT		B120

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map internal SRAM at 0x6000,0000-
; to virtual memory 0x6000,0000-
; 1M bytes of addressing, 1 entry in the MMU table	
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0x60000000			; physical memory
        LDR		r3,=0x60000000			; virtual memory
    	MOV 	r0,#1             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_ON		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN
B130
	    STR		r2,[r1],#4				; Set table value
        ADD     r2,r2,#0x100000			; Add 1MBytes addr
    	SUBS	r0,r0,#1				; Reduce number of MBytes
	    BGT		B130

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical FLASH at 0x4000,0000- Controled by CS0
; to virtual memory 0x4000,0000-
; 16M bytes of addressing, 16 entry in the MMU table	
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0x40000000			; physical memory
        LDR		r3,=0x40000000			; virtual memory
    	MOV 	r0,#16             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_ON		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN
B140
	    STR		r2,[r1],#4				; Set table value
        ADD     r2,r2,#0x100000			; Add 1MBytes addr
    	SUBS	r0,r0,#1				; Reduce number of MBytes
	    BGT		B140

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; map physical 0x4400,0000- Controled by CS1
; to virtual memory 0x4400,0000-
; 64M bytes of addressing, 64 entry in the MMU table	
; cache on, write buffer on
; r0 - number of MBytes
; r1 - translation table starting address
; r2 - physical memory starting address
; r3 - virtual memory starting address
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

        LDR     r1,=MMU_TRANS_TABLE		; MMU table start address
        LDR     r2,=0x44000000			; physical memory
        LDR		r3,=0x44000000			; virtual memory
    	MOV 	r0,#64             		; number of MBytes

		MOV     r3,r3,lsr #20			; r3>>20
 		MOV     r3,r3,lsl #2			; r3<<2
 		ADD		r1,r1,r3				; Get correct entry in 
 										; MMU translation table

		ADD		r2,r2,#CACHE_WB_OFF		; Cache and WB control
		ADD		r2,r2,#SECTION_DOMAIN