lh79524_sdk_runtime_gnu.asm

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

/*;***********************************************************************
; * $Workfile:   lh79524_sdk_runtime_gnu.asm  $
; * $Revision:   1.0  $
; * $Author:   ZhangJ  $
; * $Date:   Oct 20 2004 09:10:28  $
; *
; * Project:  LH79520
; *
;
; * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh79524/bsps/sdk79524/examples/common/lh79524_sdk_runtime_gnu.asm-arc  $
; 
;    Rev 1.0   Oct 20 2004 09:10:28   ZhangJ
; Initial revision.
; 
;    Rev 1.0   Jul 09 2003 09:09:08   LiJ
; Initial revision.
; 
; *  COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
; *                         CAMAS, WA
;**********************************************************************
;
; This code performs all the initialization required before
; branching to the main C application code.  It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code.
*/
    /*.section  ".reset", text   */
    
/* Some standard definitions... */

.equ    MODE_USR    ,0x10
.equ    Mode_FIQ    ,0x11
.equ    Mode_IRQ    ,0x12
.equ    Mode_SVC    ,0x13
.equ    Mode_ABT    ,0x17
.equ    Mode_UNDEF  ,0x1B
.equ    Mode_SYS    ,0x1F            /* only available on ARM Arch. v4 */
.equ    I_Bit       ,0x80
.equ    F_Bit       ,0x40

/*  Locations of our memory system */
.equ    MEMORY_Limit    ,0x22000000  
/*          
; = Total 32M SDRAM on LPD board, end of memory is 0x01ff,ffff
; memory 0x20000000 to 0x21ffffff is mirror of memory
; 0x0 to 0x01ffffff
*/
.equ    Stack_Limit     ,MEMORY_Limit - 0x10 
.equ    SVC_Stack       ,Stack_Limit             /* = 0x200 bytes */
.equ    ABT_Stack       ,SVC_Stack - 0x200       /* = 0x200 bytes */
.equ    UNDEF_Stack     ,ABT_Stack - 0x200       /* = 0x200 bytes */
.equ    IRQ_Stack       ,UNDEF_Stack - 0x200     /* = 0x200 bytes */
.equ    FIQ_Stack       ,IRQ_Stack - 0x200       /* = 0x200 */
.equ    USR_Stack       ,FIQ_Stack - 0x200       /* = XXX bytes */           
                
    .text

    .code 32
    .global _runtime            /* export variable  */
    .extern c_entry         /* external C program entry point */
    .extern __rw_start      /* start of the  rw     */
    .extern __rw_end        /* end of the code section      */
    .extern __zi_start      /* start of the bss section */
    .extern __zi_end        /* end of the bss section   */
    
	.align  2
_runtime:

		LDR		r0, =.SVC_DATA
		STMIA	r0!, {r1-r14}

init_stacks:
/* --- Initialize stack pointer registers */
		MRS		r1, cpsr

/* Enter IRQ mode and set up the IRQ stack pointer */
        MOV     r0, #Mode_IRQ
        orr     r0,r0,#I_Bit
        orr     r0,r0,#F_Bit                    /* No interrupts */
        MSR     cpsr_c, r0
        LDR     sp, =IRQ_Stack

/* Enter FIQ mode and set up the FIQ stack pointer */
        MOV     r0, #Mode_FIQ
        orr     r0,r0,#I_Bit
        orr     r0,r0,#F_Bit                    /* No interrupts */
        MSR     cpsr_c, r0
        LDR     sp, =FIQ_Stack

/* Enter ABT mode and set up the ABT stack pointer */
        MOV     r0, #Mode_ABT
        orr     r0,r0,#I_Bit
        orr     r0,r0,#F_Bit                    /* No interrupts */
        MSR     cpsr_c, r0
        LDR     sp, =ABT_Stack

/* Enter IRQ mode and set up the IRQ stack pointer */
        MOV     r0, #Mode_UNDEF
        orr     r0,r0,#I_Bit
        orr     r0,r0,#F_Bit                    /* No interrupts */
        MSR     cpsr_c, r0
        LDR     sp, =UNDEF_Stack

/* Set up the SVC stack pointer last and return to SVC mode */
        @MOV     r0, #Mode_SVC
        @orr     r0,r0,#I_Bit
        @orr     r0,r0,#F_Bit                    /* No interrupts */
        @MSR     cpsr_c, r0
        MSR     cpsr_c, r1
        @LDR     sp, =SVC_Stack 

/* Zero Initialize memory */
        ldr     r2, =bssStart
        ldr     r3, =bssEnd
        ldr     r1, [r2]
        ldr     r0, [r3]
        SUB     r0, r0, r1      /* RW section length in r0 */
        MOV     r3,#0
        CMP     r0, #0
        BEQ     L91
L90:
        STR     r3, [r1], #4
        SUBS    r0, r0, #4
        BGT     L90
L91:

/* initialize the heap */

/* enable the Cache and Write buffer */
        MOV     r1,#0x7C    /* enable cache, enable write buffer */
        MCR     p15, 0, r1, c1, c0, 0

/* --- Now we enter the main C application code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
*/

/*; DO THE REST OF THINGS IN C UNLESS IT IS NOT POSSIBLE */

        BL      c_entry 

/* If above subroutine ever returns, just sit in an endless loop */
here:   
		@B       here

		LDR		r0, =.SVC_DATA
		LDMIA	r0!, {r1-r14}
		MOV		pc, r14		@ return to caller


__gccmain:
    mov pc, lr          /* return - gnu specific    */
exit:
    b   exit            /* on exit sit and spin     */


sIRQ_Stack:
        .word IRQ_Stack
sFIQ_Stack:
        .word FIQ_Stack
sABT_Stack:
        .word ABT_Stack
sUNDEF_Stack:
        .word UNDEF_Stack

sSVC_Stack:
        .word SVC_Stack


bssEnd:
        .word   __zi_end
bssStart:
        .word   __zi_start
rwStart:
        .word   __rw_start
rwEnd:
        .word   __rw_end

        
.SVC_DATA:	
        .space 	100        @ reserve 100 bytes
        
        .end