lh79524_sdk_runtime_arm.s

SHARP_ARM720T_LH79524/5软件开发包_支持TFT_LCD_NAND_FLASH_ETH_USB

;***********************************************************************
; * $Workfile:   lh79524_sdk_runtime_arm.s  $
; * $Revision:   1.0  $
; * $Author:   ZhangJ  $
; * $Date:   Oct 20 2004 09:10:28  $
; *
; * Project:  LH79520
; *
;
; * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh79524/bsps/sdk79524/examples/common/lh79524_sdk_runtime_arm.s-arc  $
; 
;    Rev 1.0   Oct 20 2004 09:10:28   ZhangJ
; Initial revision.
; 
;    Rev 1.0   Jul 09 2003 09:09:08   LiJ
; Initial revision.
; 
; *  COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
; *                         CAMAS, WA
;**********************************************************************/
;
; This code performs all the initialization required before
; branching to the main C application code.  It defines the
; ENTRY point, initializes the Stack Pointers for each mode,
; copies RO code and RW data from ROM to RAM and zero-initializes
; the ZI data areas used by the C code.
;

                AREA    LH79520_RUNTIME, CODE, READONLY

; Some standard definitions...

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UNDEF      EQU     0x1B
Mode_SYS        EQU     0x1F            ; only available on ARM Arch. v4

I_Bit           EQU     0x80
F_Bit           EQU     0x40

; Locations of our memory system
MEMORY_Limit    EQU     0x22000000              
; = Total 32M SDRAM on LPD board, end of memory is 0x01ff,ffff
; memory 0x20000000 to 0x21ffffff is mirror of memory
; 0x0 to 0x01ffffff
Stack_Limit     EQU     MEMORY_Limit - 0x10 
SVC_Stack       EQU     Stack_Limit             ; = 0x400 bytes
ABT_Stack       EQU     SVC_Stack - 0x400       ; = 0x200 bytes
UNDEF_Stack     EQU     ABT_Stack - 0x200       ; = 0x200 bytes
IRQ_Stack       EQU     UNDEF_Stack - 0x200     ; = 0x200 bytes
FIQ_Stack       EQU     IRQ_Stack - 0x200       ; = 0x200
USR_Stack       EQU     FIQ_Stack - 0x200       ; = XXX bytes          
                

        IMPORT  |Image$$ER_RO$$Base|
        IMPORT  |Image$$ER_RO$$Length|
        IMPORT  |Load$$ER_RO$$Base|
        IMPORT  |Image$$ER_RW$$Base|
        IMPORT  |Image$$ER_RW$$Length|
        IMPORT  |Load$$ER_RW$$Base|
        IMPORT  |Image$$ER_ZI$$Base|
        IMPORT  |Image$$ER_ZI$$Length|
        IMPORT  |Image$$ER_ZI$$ZI$$Length|


        EXPORT  _runtime
        ENTRY
_runtime

		LDR		r0, =SVC_DATA
		STMIA	r0!, {r1-r14}


init_stacks
; --- Initialize stack pointer registers

		MRS		r1, cpsr
; Enter IRQ mode and set up the IRQ stack pointer
        MOV     r0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
        MSR     cpsr_c, r0
        LDR     sp, =IRQ_Stack

; Enter FIQ mode and set up the FIQ stack pointer
        MOV     r0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        MSR     cpsr_c, r0
        LDR     sp, =FIQ_Stack

; Enter ABT mode and set up the ABT stack pointer
        MOV     r0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
        MSR     cpsr_c, r0
        LDR     sp, =ABT_Stack

; Enter UNDEF mode and set up the IRQ stack pointer
        MOV     r0, #Mode_UNDEF:OR:I_Bit:OR:F_Bit ; No interrupts
        MSR     cpsr_c, r0
        LDR     sp, =UNDEF_Stack

; Set up the SVC stack pointer last and return to SVC mode
;        MOV     r0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        MSR     cpsr_c, r1
;        LDR     sp, =SVC_Stack

; Zero Initialize memory
        MOV     r3, #0
        LDR     r0, =|Image$$ER_ZI$$ZI$$Length|
        LDR     r2, =|Image$$ER_ZI$$Base|
        CMP     r0, #0
        BEQ     %F91
90
        STR     r3, [r2], #4
        SUBS    r0, r0, #4
        BGT     %B90
91


;initialize the heap
        IMPORT  _init_alloc
        IMPORT  ||Image$$ER_ZI$$ZI$$Limit||
        LDR     r0,=||Image$$ER_ZI$$ZI$$Limit||
        LDR     r1,=USR_Stack-0x10000       ;64k user stack
        BL      _init_alloc        

; enable the Cache and Write buffer
        MOV     r1,#0x7C    ;enable cache, enable write buffer
;        MCR     p15, 0, r1, c1, c0, 0

; --- Now we enter the main C application code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
        IMPORT  c_entry

; DO THE REST OF THINGS IN C UNLESS IT IS NOT POSSIBLE

        BL      c_entry ; in C_main.c

; If above subroutine ever returns, just sit in an endless loop
;here    B       here

		LDR		r0, =SVC_DATA
		LDMIA	r0!, {r1-r14}
		MOV		pc, r14	; return to caller

        EXPORT  __main  ; defined to ensure C runtime lib is not linked in
__main              ; defined to ensure C runtime lib is not linked in
        
        mov     pc, #0x0     ;if there is return from main, reset


;        AREA    LH79520_RUNTIME, DATA, READWRITE
DATA_RESERVE	SPACE	100
				MAP		DATA_RESERVE
SVC_DATA		FIELD	20
              
     
        
        
        
        END