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Date: Wed, 15 Jan 1997 01:31:24 GMTServer: NCSA/1.4.2Content-type: text/htmlLast-modified: Wed, 04 Sep 1996 19:19:54 GMTContent-length: 3679<HTML><HEAD><TITLE>Dissertation Abstract</TITLE></HEAD><body bgcolor=#ffffff text=#000000><BODY><!WA0><A HREF = "http://www-cse.ucsd.edu/users/iharris/images/diss_abs.ps">Click here</A> to download the postscript version of this statement.<p><h1>Abstract of Dissertation Prospectus</h1><!WA1><IMG align=middle SRC="http://www-cse.ucsd.edu/users/iharris/images/line1.gif"><p>As device sizes continue to diminish, the chip gate-to-pin ratioincreases, reducing chip testability. The strong effect of testabilityon production cost makes it imperative that it be well integrated intothe VLSI design process. High-level synthesis automates the designprocess, allowing design alternatives to be explored more efficiently.The importance of testability necessitates exploration of test optionsduring the design process as early as possible.<p>The increasing complexity of chip circuitry increases the cost ofproduction by causing test time to rise, thereby reducing productionthroughput. For this reason, it is necessary to generate designs whichdeliver high fault coverage with low test time. Chip performance is acritical constraint for any high speed application area such as realtime digital signal processing which is used in almost any multi-mediaapplication. The inclusion of testability into a design often causes asevere performance degradation. Since testability is alsoimportant for such designs, it is necessary to include testabilitywith minimal impact on the chip performance. Low test time and reducedperformance degradation must be achieved simultaneously during thedesign of a testable system.<p>The chief component of test time is the degree of allowable testconcurrency between the testing of different parts of the chip. Twochip components may not be tested concurrently if the tests whichexamine the two components share hardware. In order to minimize testtime, designs must be generated which allow tests to be defined whichshare hardware as little as possible. Performance is reduced when testregisters are inserted into delay-critical paths of the design. Testregisters must be inserted to ensure testability, while avoiding thedelay critical paths of the circuit. Once a testable design has beengenerated, tests must be defined for that design which areparallelizable. <p>I will design a system which performs three tasks with the goal of testtime minimization:<ul><li>Definition of a circuit which is testable with a high degree oftest concurrency, from a behavioral description.<li> Insertion of test registers into the defined circuit to allowthe definition of parallelizable tests while minimizing the degradationof chip performance.<li> Definition of a highly concurrent BIST test plan for the circuit.</ul>The work presented here will be applied to a wide range of Built-InSelf-Test (BIST) methodologies. By altering the area overheadlimitation, the designs produced by this system can range from fullycentralized BIST, where all chip components are tested by the same testregisters, to partially distributed BIST, where the degree of testregister sharing is restricted. <p>The cost of chip testing has become a large fraction of chipproduction cost and the effect of test register insertion onperformance is critical for any high speed application. The needfor an integrated system which considers test time and performancereduction due to testability at the earliest stage of design is clear.Previous efforts to increase testability neither integrate thedifferent levels of testable circuit design nor directly address theproblem of minimizing test conflicts and performance degradation in acomputationally efficient way.<p><!WA2><IMG align=middle SRC="http://www-cse.ucsd.edu/users/iharris/images/line1.gif"><p></BODY></HTML>⌨️ 快捷键说明
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