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📄 http:^^www.cs.ucsb.edu^~cappello^personal^presentations.html

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Date: Wed, 15 Jan 1997 00:34:31 GMT
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<html><head><title>Cappello:Presentations</title></head><body><h1><center>Presentations</center></h1><hr>This is a list of presentations other than those given at a conference with a published proceedings. In each item, the presentation was given bythe author whose name is <strong>emboldened</strong>.<ol><li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Unifying Systolic Design with Linear Transformations of Spacetime.<em>Electrical Engineering-Systems Department Seminar, University of SouthernCalifornia</em>,  Los Angeles, Feb. 1983.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Unifying Systolic Design with Linear Transformations of Spacetime.<em>Office of Naval Research Workshop on VLSI Architectures forSpecial-purpose Machines</em>,Mt. Ada Conference Center, Catalina, CA, Mar. 1984.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Mapping Gaussian Elimination onto Multiprocessor Architectures.<em>Computer Science Department, Yale University</em>,New Haven, CT, Aug. 1985.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Systolic Design for Digital Signal Processing.<em>Symposium on the Impact of VLSI on Signal Processing</em>,Communications Research Laboratory, McMaster University, Hamilton, Ontario,CANADA, Oct. 1985.<li> (<strong>Selected</strong>)  <strong>Peter Cappello</strong>.Solving Dense Linear Systems on a Hypercube Automaton.<em>SIAM Conf. on Parallel Processing for Scientific Computing</em>,Norfolk, VA, Nov. 1985.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>.An FIR Filter Tissue.<em>Office of Naval Research Workshop on Ultra Submicron Architectures</em>,Pasadena, Dec. 1985.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Systolic Design for Digital Signal Processing.<em>IEEE Philadelphia Section Seminar on Systolic Parallel Architectures forSignal Processing</em>, University of Pennsylvania, Apr. 1986.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>.Languages and Tools for Systolic Computation.<em>Office of Naval Research Workshop on Systolic Algorithms andArchitectures</em>, Hilton Head, SC, Dec. 1986.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>. Representing Systolic Computation.<em>Dept. of Electrical Engineering, UCLA</em>, Nov. 1987.<li> <strong>Peter Cappello</strong>. A New Bijection between Natural Numbers and Rooted Trees.<em>4th SIAM Conf. on Discrete Mathematics</em>, San Francisco, June 1988.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>.A VLSI layout for a Dadda Multiplier.<em>Computer Engineering Seminar, University of Southern California</em>,Los Angeles, March 1989.<li> <strong>Peter Cappello</strong> and &Ccedil;etin K. Ko&ccedil;.Decomposing Chinese remaindering for systolic arrays.<em>SIAM Ann. Meeting</em>, San Diego, July 1989.<li> Peter Cappello, <strong>&Ccedil;etin K. Ko&ccedil;</strong>, and Efstratios Gallopoulos.Systolic computation of interpolating polynomials.<em>SIAM Conf. on Parallel Processing for Scientific Computing</em>,Chicago, Dec. 1989.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong>.A Processor-Time Minimal Systolic Array for Matrix Product.<em>Computer Science Colloquium, University of Oregon</em>, Eugene, Apr. 1990.<li> <strong>Yoav Yaacoby</strong> and Peter Cappello.Decoupling the dimensions of a system of affine recurrence equations.<em>The 6th Haifa Matrix Theory Conference</em>,The Technion, Haifa, ISRAEL, June 1990.<li> <strong>&Ouml;mer Egecioglu</strong> and Peter Cappello.A Bijection with Applications to Asymptotic Properties of Rooted Trees.<em>6th SIAM Conf. on Discrete Mathematics</em>,Vancouver, BC, June 1992.<li> (<strong>Invited</strong>)  <strong>Peter Cappello</strong> and Chris Scheiman.A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms.<em>Electrical and Computer Engineering Seminar</em>, Oregon State University,Corvallis, OR, Feb. 1993.</ol><hr></body></html>

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