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Date: Tue, 14 Jan 1997 23:23:42 GMT
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<!doctype html public "-//IETF//DTD HTML//EN"><HTML><HEAD><TITLE>Homework 4</TITLE><META NAME="GENERATOR" CONTENT="Internet Assistant for Word 1.0Z"><META NAME="AUTHOR" CONTENT="Samir Das"></HEAD><BODY><H3>Homework 4 </H3><H3>Due Nov 5, 1996</H3><OL><LI> (10 points) Assume that in DLX (Figure 3.44) <I>all</I>arithmetic functional units (such asthe integer ALU, FP adder, Int/FP multiplier and the Int/FP divider)are fully pipelined. All functional units are completely independent,i.e., they do not share any of the stages. All functional unitsconsume their operands at the very first EX stage. Argue thatif there are <I>n</I> stages in a functional unit, the latencyfor that unit producing a value and any unit (same or different)consuming the same value is <I>n-1</I>; however, the latency forthat unit producing a value and a store instruction consumingthe same value as <I> memory data </I> is <I>n-2.</I> (<B>Hint:</B> Theanswer is in the book.) <p>Will the same latencies be true if operandsare <I>not </I>consumed at the very first EX stage? Explain.<p><LI> (10 points) Solve problem 4.1.<p><LI> (15 points) Solve problem 4.10.<p><LI> (10+15+20+20 points) Solve problems 4.14 (a), (b), (c) and (g). <p><b> Hints: </b> For parts (a) and (b) assume the classic pipeline as inFigure 3.44 with latencies as suggested. Assume all possible forwarding. <p>For part (c), notice that inscoreboarding as described in the text, the MEM stage is conspicuouslyabsent. Since we need to follow the text, assume that memory accessesare made in the EX cycle for load/store in addition to the effectiveaddress calculation. So any integer operation including loads take only4 cycles (ID1,ID2,EX,WB) in the absence of any stalls. Do not track thebranch as suggested. Assume that it is taken and issue instructions from the next iteration if possible. For scoreboarding the only forwarding you can assume is via the register file, i.e., you can write/readthe value in the same cycle. Thus to be consistent with given latenciesassume that the number of EX stages for MULTD and ADDD is 3 (convinceyourself on this point). You will need this information to figure outthe instruction execution status when SGTI reaches WB stage.<p>For part (g), just concentrate on the maximum rate you can issueinstructions and try to get 2 issues per cycle.</OL></BODY></HTML>⌨️ 快捷键说明
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