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<html><head><!-- This document was created from RTF source by rtftohtml version 2.7.5, extended by rtftoweb version 1.6. --><title>Dr. Pradhan</title></head><body><p><b>Name:</b> Dhiraj K. Pradhan <p><b>Title:</b> COE Endowed Chair in Computer Science<p><p><b>EDUCATION:</b><p>Ph.D. Electrical Engineering, University of Iowa, 1972<p>M.S. Electrical Engineering, Brown University, 1970<p>B.S. Electrical Engineering, Annamalai University, 1969<p><p><b>EXPERIENCE:</b><p><i>Educational: </i><b>COE Endowed Chair Professor</b>, Computer Science,Texas A&M University, January 1992-present; <b>Professor</b>, Department ofElectrical and Computer Engineering, University of Massachusetts, January1983-January 1992; <b>Associate Professor</b>, School of Engineering, OaklandUniversity, September 1978-December 1982; <b>Research Associate Professor</b>,Stanford University, June 1979-August 1979; <b>Associate Professor</b>,Department of Computer Science, University of Regina, September 1973-July1978.<p><i>Industrial</i>: Staff Engineer, IBM, Systems Development Laboratory,October 1972-August 1983.<p><i>Consulting: </i>Consultant to Mitre, CDC, IBM, AT&T, DEC and DataGeneral, 1982-present.<p><i></i><p><b>HONORS & PROFESSIONAL ACTIVITIES:</b><p><i>Professional Activities</i>: <b>Program Chair</b>, 1st and 2nd IEEEInternational On-Line Testing Workshop, 1995-96; <b>Program Committee Member</b>, Fault-TolerantComputing Symposium and Computer Architecture Conference and VLSI Test Design,1995; <b>Editor</b>, IEEE Transactions on Computers, 1991-present;<b>Editor</b>, IEEE Computer Society Press, 1990-present; <b>AssociateEditor</b>, Journal of Circuits, 1989-present; <b>Editor</b>, Journal of Electronic Testing, 1988-present; <b>WorkshopChair,</b> IEEE Workshop on Fault-tolerant Parallel and Distributed Systems,1994; <b>General Chair,</b> IEEE Workshop on Fault-Tolerant Parallel andDistributed Systems, 1994; <b>Program Chair</b>, 10th and 11th IEEE VLSI TestSymposium, 1992 and 1993; <b>IEEE Distinguished Visitor</b>, Computer Society,1990-93; <b>ACM Lecturer</b>, 1990-92; <b>Advisory Committee,</b> IEEETechnical Committee on Parallel Processing, 1992; <b>Conference Chair</b>, 22ndInternational Symposium on Fault-Tolerant Computing, 1992; <i></i><p><i>Awards:</i> </b>IEEE Meritorious Computer Society Service Award, 1994;<b>Best Paper Award,</b> VLSI Design Conference, 1994; <b>Humboldt Distinguished Senior Scientist Award</b>, Germany, 1990, <b>Fellowof IEEE, </b>l987.<p><p><b>RESEARCH INTERESTS/AREAS OF EXPERTISE:</b>Fault-Tolerant Computing, VLSI Testing, Computer Architecture,Computer Aided Design <p><p><b>RESEARCH SUPPORT:</b> <b>NRC</b> 1973-79, <b>AFOSR</b>, 1985-95 , multiple grants; <b>NSF, </b>1982-92 , multiple grants'<b>NSF</b>, 1992-95; <b>ONR</b>, 1991-96;<b>NSF</b>, 1994-95; <b>NSF,</b> 1994-97;<b>Texas </b>1994-96; <b>Texas , </b>1994-95.<p><p><b>TEXT BOOKS:</b><p><I>Fault-Tolerant Systems Design</I>, Prentice-Hall, Inc. April 1996.<p>IC <i>Manufacturability: The Art of Process and Design Integration,</i> (withJ. de Gyvez), IEEE Press, 1996.<p><i>Fault-Tolerant Computing:</i> <i>Theory and Techniques</i> , (Editor andCo-Author), Vol. I and II, Prentice-Hall, Inc., May l986 (Second Edition toappear 1991).<p><p><b>SELECTED PUBLICATIONS:</b><p><b>Journals:</b><p>"Issues in Fault Tolerant Memory Management," (with N. Bowen), <i>IEEETransactions on Computers</i>, to appear.<p>"On-Line Detection Circuit in Built-in Self-Test for Achieving ZeroAliasing," (with S. Gupta), <i>IEEE Transactions on Computers</i>, accepted.<p>"Can Concurrent Checkers Help BIST?", (with S. Gupta), <i>IEEE Transactions onComputers</i>, to appear.<p>"Efficient Logic Verification in a Synthesis Environment," (with W. Kunz, andS. Reddy), <i>IEEE Transactions on Computer-Aided Design</i>, accepted.<p>"A Scheme to Reduce Test Application Time in Circuits with Full Scan," (with J.Saxena), <i>IEEE Transactions on Computer-Aided Designs,</i>, accepted.<p>"The Effect of Program Behavior on Fault Observability," (with N. Bowen),<i>IEEE Transactions on Computers, </i>accepted.<p>"Processor Allocation in Hypercube Multicomputers: Fast and EfficientStrategies for Cubic and Non-Cubic Allocation," (with D. Das Sharma),<i>IEEE Transactions on Parallel and distributed Systems</i>, toappear.<p>"The Hierarchical Full-Map Directory Scheme: Protocol and Performance," (withY.C. Maa and D. Thiebault), <i>IEEE Transactions on Computers</i>, toappear.<p>"A Fault Tolerant Hybrid Memory Structure & Memory Management Algorithm,"(with N. Bowen), <i>IEEE Transactions on Computers</i>, Vol 44(3) pp. 408-418,March 1995.<p>"Static and Dynamic Location Management in Distributed Mobile Environments,"(with P. Krishna, and N.H. Vaidya), <i>Computer Communication</i>(special issue on Mobile Computing), 1995.<p>"A Survey of Fault-Injection Experimentation for Validating Computer SystemDependability," (with J. Clark), <i>COMPUTER</i>, June 1995, pp. 47-56.<p>"Degradable Byzantine Agreement," (with N.H. Vaidya), <i>IEEE Transactionson Computers</i>, Vol. 44(1), pp. 146-150, January 1995.<p>"Safe System Level Diagnosis," (with N. Vaidya), <i>IEEE Transactions</i>, Vol.43(3) pp. 367-370, March l994.<p>"Recursive Learning: A Precise Implication Procedure and its' application toTest Verification and Optimization," (with W. Kunz ), <i>IEEE Transactionson Computer-Aided Design</i>, September 1994.<p>"Roll Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture," (withN. Vaidya), <i>IEEE Transactions on Computers</i>, Vol. 43(10), pp.1163-1174, October 1994.<p>"Yield Optimization of Redundant Multimegabit RAM's Using the Center-SatelliteModel," (with D. Das Sharma and F. Meyer), <i>IEEE Transactions on VLSIsystems</i>, December 1993.<p>"Communication Structures in Fault-Tolerant Distributed Systems," (with F. J.Meyer) <i>NETWORKS</i>, vol. 23, pp. 379-389, 1993.<p>"The Hyper-deBruijn Networks: Scalable Versatile Architecture," (with E.Ganesan), <i>Transactions on Parallel and Distributed Systems</i>, Vol.4(9), pp. 962-978, September 1993.<p>"The Effect of Memory-Management Policies on System Reliability," (with N.Bowen), <i>IEEE Transactions on Reliability</i>, </b>Vol. 42(3), pp.375-383, September 1993.<p>"Processor and Memory Based Checkpoint and Rollback Recovery," (with N. Bowen),<i>COMPUTER</i>, pp. 22-31, February 1993.<p>"Modeling Live and Dead Lines in Cache Memory Systems," (with D. Thiebault andA. Mendelson), <i>IEEE Transactions on Computers</i>, Vol. 2(1), pp.1-14, January 1993.<p>"A New Algorithm for Rank-Order Filtering and Sorting," (with B. Kar),<i>IEEE Transactions on ASSP</i>, vol. 41(8), pp. 2688-2694, August1993.<p>"Survey of Checkpoint and Rollback Recovery Techniques," (with N. Bowen)<i>COMPUTER</i>, </b>Vol. 26(2), pp. 22-31, February 1993.<p>"Accelerated Dynamic Learning for Test Pattern Generation in CombinationalCircuits," (with W. Kunz), <i>IEEE Transactions on Computer-AidedDesign</i>, " Vol., 12(5), pp. 684-694, May 1993.<p>"Fault-Tolerant Design Strategies for High Reliability and Safety," (with N.Vaidya), <i>IEEE Transactions on Computers</i>, Vol. 42(10), pp.1195-1206, October l993.<p><p><b>CONFERENCES:</b><p>"LOT: Logic Optimization with Testability - New Transformations using RecursiveLearning," (with M. Chatterjee and Wolfgang Kunz), ICCAD'95. San Jose, CA,November 5-9, l995.<p> "Performance and Reliability Assessment of I/0 Subsystems," (with F. Meyerand N. Vaidya), 4th International Workshop on Evaluation Techniques forDependable Systems, October 2-3, l995.<p>Enhanced Tool for Evaluating the Dependability of Fault-Tolerant ComputingSystems, 4th International Workshop on Evaluation Techniques for DependableSystems, October 2-3, l995.<p>"Routing in Mobile Wireless Networks," (with P. Krishna, M. Chatterjee and N.Vaidya), USENIX Symposium on Mobile and Location-Independent Computing, Aprill995.<p>"On Improving OBDD-Based Verification in a Synthesis Environment," (with S.Reddy and W. Kunz), 32nd Design automation Conference, June l995.<p>"A Cluster-based Approach for Routing in Ad-Hoc Networks, ," (with P. Krishna,M. Chatterjee and N.H. Vaidya) USENIX Symposium on Location Independent andMobile Computing, pp. 1-10, April 1995.<p>"Modified Tree Structure for Location Management in Mobile Environments," (withS. Dolev), IEEE Infocom'95 , Special Topics, April 2-6, 1995.<p>"Providing Seamless Communications in Mobile Wireless Networks," (with P.Krishna, B. Bakshi and N. Vaidya), 1st International Conference on MobileComputers and Networking, Berkeley, CA, November 14-15, 1995.<p>"Novel Verification Framework Combining Structural and OBDD Methods in aSynthesis Environment," (with S. Reddy, and W. Kunz), 32nd Design AutomationConference, San Francisco, CA, pp. 414-419, June 12-16, 1995. <p>"Design Methodology for Test Synthesis in BIST," (with M. Chatterjee), IEEEBIST/DFT Workshop, March 1995.<p>"A Novel Pattern Generator for NearPerfect Fault Coverage," (with M.Chatterjee), IEEE VLSI Test Symposium, pp. 417-425, April 1995.<p>"ATPG-based Transformations for Random-Pattern Testable Logic Synthesis," (withM. Chatterjee and W. Kunz), IEEE/ACM Intl. conference on CAD, November l995.<p>"Functional Learning: A New Approach to Learning in Digital Circuits," (withMukherjee and Jain), l2th IEEE VLSI Test Symposium, April l994.<p>"Location Management in Distributed Mobile Environment," (with P. Krishna, andN.H. Vaidya), <i>Proc. of 3rd Intl. Conf. on Parallel and DistributedInformation Systems, </i>pp. 81-88, September 1994.<p>"New Pseudo-Random Test Pattern Generators for Stuck-at and Transition Faults,"(with M. Chatterjee), 12th <i>IEEE VLSI Test Symposium</i>, April 25-29,1994.<p>"Bit-Serial Generalized Median Filters," (with K. Bar), <i>IEEE InternationalSymposium for Computer-Aided Systems, </i>1994.<p>"Job Scheduling in Mesh Multicomputers," (with D. Das Sharma), <i>1994International Conference on Parallel Processing,</i> Vol. II, pp. 251-258.<p>"Subcube Level Time-Sharing in Hypercube Multicomputers," (with D. Das Sharma,and G. Holland), <i>1994 International Conference on Parallel Processing,</i>Vol. II, pp. 134-142.<p>"GLFSR-A New Test Pattern Generator for BIST," (with M. Chatterjee), <i>1994International Test Conference,</i> pp. 481-490.<p>"Recovery in Multicomputers with Finite Error Detection Latency," (with P.Krishna, and N.H. Vaidya), <i>Proc. of Intl. Conference on ParallelProcessing,</i> pp. 206-210, August 1994.<p><p>Patents<p>"Easily Testable High Speed Architectures for Large RAMs", U. S. Patent No.4,833,677, May 23, 1989.<p>"Method of Circuit Verification and Multi-Level Circuit Optimization Based onStructural Implications, "U.S. Patent No. 08,263,721, June 21, 1994.<p><p></body></html>⌨️ 快捷键说明
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