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performance than set-associative ones despite having larger
miss ratios, and provided insight into cache design with
the 3C model which separates the compulsory, capacity,
and conflict components of the miss ratio.
<p>
In the area of cache design,
Goodman showed how Static-Column DRAMs (SCRAMs)
can be used as a "poor man's"
cache, providing some of the benefits of cache memory without using SRAM.
Hill and Wood participated in the first studies of 
multi-megabyte cache design (which some contemporaries
criticized as never to become practical).
Sohi showed why processors would have to change from using (then prevalent)
blocking caches to non-blocking caches as they became more
aggressive in exploiting ILP.
<p>
Each one of these contributions can be found, to varying extents,
in modern computer systems.
For example, both Sun Microsystems and Compaq have built
computers containing SCRAM caches,
direct-mapped caches are now at least as common as set-associative ones,
multi-megabyte second level caches are widely used,
and most recently-announced superscalar microprocessors
use non-blocking caches.
<h3>Multiprocessor Systems</h3>
<p>
In multiprocessor systems, Goodman published the first paper
describing a snooping cache coherence protocol.
Snooping cache protocols enabled 
the construction of shared-bus multiprocessors,
also called symmetric multiprocessors, in the marketplace.
Such multiprocessors were one of the earliest
available general-purpose multiprocessor systems and
have become the most common form of multiprocessing available today.
Among the earliest snooping-cache systems were the
Sequent Balance and the Encore Multimax,
both of which were directly influenced by the Wisconsin work.
Some microprocessors, such as the Motorola 88000,
have implemented almost exactly the write-once protocol as
described by Goodman.  Recent multiprocessor workstations
and servers, such as those manufactured by Sun Microsystems,
also use snooping cache protocols.
<p>
Goodman and Sohi contributed to the IEEE standard 1596
Scalable Coherent Interface,
the first commercial-grade directory-based coherence scheme.
Goodman contributed extensively to the basic cache coherence protocol,
and to the development of options for achieving higher performance.
Goodman and Sohi were primary contributors to the development of
protocols for large numbers of caches (kiloprocessor extensions).
The Convex Exemplar system is the first commercial system
to use the Scalable Coherent Interface,
but many other systems are currently under development,
including at Unisys and IBM.
<p>
Goodman and Vernon developed the first synchronizing prefetch primitive,
which was incorporated in the SCI standard.
This technique, known as QOLB,
for synchronizing shared memory accesses,
also inspired software implementations for implementing
efficient locks that minimize network traffic during contention.
In particular, the QOLB-inspired MCS lock has become the standard
locking mechanism for shared-memory multiprocessors.
Another synchronization mechanism invented by UW researchers is a
novel technique to combine Fetch&Increment operations.
The applicability of this technique is likely to grow
as more powerful multiprocessors, with more aggressive synchronization
requirements, are built.
<p>
Another area of contributions is
memory consistency models which specify the semantics of shared memory.
Wisconsin researchers were among the first to recognize that memory
consistency was not synonymous with cache coherence.  Goodman defined
processor consistency that codified the general effect of buffering
writes.  Hill showed how weak ordering could be viewed as sequential
consistency (the strongest model) by data-race-free programs.  This
formalization and subsequent generalizations allow more sophisticated
compiler and hardware optimizations than were previously possible.  The
full industrial impact of memory consistency models has yet to be felt,
however, and probably must await the wide deployment of out-of-order
issue processors, non-blocking caches, and software/hardware hybrid
coherence solutions.
<p>
Practical research in multiprocessors is continuing at Wisconsin.
Recent research includes
contributions in the ``middle interface'': below languages and
compilers and above system software and hardware.
For example, UW researchers are developing Tempest,
a novel approach to provide support for shared-memory,
message-passing, and hybrid combinations of the two.
<p>
<h3>Enabling Technologies</h3>
The design of a computer system requires quantitative assessments
of various design criteria.  Wisconsin researchers have advanced both
theory and practice of these important enabling technologies.
Hill developed new algorithms, and software tools that use these algorithms,
for simultaneously simulating multiple alternative cache organizations.
Larus developed new techniques, and software tools using these techniques, 
for rewriting executables to profile programs.
Wood and Hill advanced the state-of-the-art of