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Date: Mon, 04 Nov 1996 23:41:47 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Tue, 18 Jun 1996 12:38:10 GMTContent-length: 3285<html><head><title> Doug Burger's Research Page </title></head><body><base href="http://www.cs.wisc.edu/~dburger/"><strong><A NAME="research">Research interests:</A></strong><ul><li> <!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~arch/uwarch">Computer architecture</a><li> Memory systems<li> Microprocessor architectures<li> Shared-memory multiprocessing<li> Parallel discrete-event simulation</ul> <p><strong>Research summary:</strong><p>My <!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><a href="http://www.cs.washington.edu/homes/lazowska/cra">research</a> is currently focused on finding ways to improve the performance of uniprocessoron-chip memories. The preliminary part of this research involves exploring the virtues ofexplicit memory management; memory-mapping part of a cache into the program's address space,or treating it as a large register file. This research is a key component of the <!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.wisc.edu/~galileo/">Galileo</a> project, which isattempting both to identify fundamental long-term limitations to improved performance and to propose near- and far-term solutions. This is joint work with <!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.cs.wisc.edu/~alain/alain.html">Alain Kägi</a>, <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><A HREF="http://www.cs.wisc.edu/~kaxiras/kaxiras.html">Stefanos Kaxiras</A>, and<!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href="http://www.cs.wisc.edu/~goodman/goodman.html">Jim Goodman</a>.<p>Related work in which I am currently involved is analyzing the efficiencies of cachesfor a wide variety of programs. Determining the efficiency of a cache (i.e., how muchof the cache contains useful data) and breaking the (in)efficiency into separatecategories will hopefully yield insight into some of the fundamental problems with thecurrent caching model.<p>I am also involved with a beginning effort to evaluate the performance of the Scalable CoherentInterface by directly comparing it with an implementation of the Typhoon protocol processor,through simulation on the Wisconsin Wind Tunnel. Another ongoing project is a studyof the scalability of the base SCI protocol (including the standard options), simulatingSCI machines comprised of thousands of high-performance processors, running realscientific workloads. This work is being performed on the National Center forSupercomputing Applications' 512-node Thinking Machines CM-5.<p>Some of my previous work involved studies of SCI, evaluating performance benefits of a range ofoptimizations (with <!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href="http://www.cs.wisc.edu/~alain/alain.html">Alain Kägi</a>) and studying a preliminary design of a MESI/SCI interface chip. I also investigated context schedulingissues for shared-memory multiprocessors, specifically with regard to virtual memory overheads (with <!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href="http://www.cs.wisc.edu/~hyder/hyder.html">Rahmat Hyder</a>, <!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href="http://www.cs.wisc.edu/~david/david.html">David Wood</a>, and <!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><a href="http://www.cs.wisc.edu/~pubs/faculty-info/bart.html">Bart Miller</a>). My main contribution tothe <!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><A HREF="http://www.cs.wisc.edu/~wwt/">Wisconsin Wind Tunnel</A> project was the developmentof its network simulator and the subsequent evaluation of related issues, performed jointlywith David Wood.<p>Last modified: Tue Jun 18 07:37:00 1996 by Doug Burger<ADDRESS><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><A HREF="mailto:dburger@cs.wisc.edu">dburger@cs.wisc.edu</A><BR></ADDRESS></BODY></html>⌨️ 快捷键说明
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