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Date: Tue, 05 Nov 1996 20:53:14 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Tue, 05 Nov 1996 05:39:25 GMTContent-length: 5780<htmli<head><title> Architecture Seminar Schedule </title></head><!--<body bgcolor="#ccccee" text="#000000" link="#551a8b" vlink="#2e8b57">--><body background = "o027.jpg"><center><h2><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><A HREF="http://www.cs.wisc.edu/~arch/uwarch">Computer Architecture</A> Colloquium</h2><p>Architecture colloquia will be held in CS 1325, 4-5 pm, Tue(unless specified otherwise).<br>Click on the title of a talk to view the abstract, if available.<p><br><table border=2><tr><td align=center><b>Date</b></td><td align=center valign=top><b>Speaker</b></td><td align=center valign=top><b>Title</b></td></tr><!--<tr><td align=center valign=top>---DATE---</td><td align=center valign=top><em><a href"---URL---">---NAME---</a></em><br>UW-Madison</td><td align=center valign=top>---Title of Talk---</a></td></tr>--><tr><td align=center valign=top>Sep 3</td><td align=center valign=top><em>Nothing scheduled</a></em><td align=center valign=top>Nothing scheduled</a></td></tr><tr><td align=center valign=top>Sep 10</td><td align=center valign=top><em><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><a href = "http://www.cs.wisc.edu/~markhill/markhill.html"> Mark Hill,<!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href = "http://www.cs.wisc.edu/~larus/larus.html"> James Larus,<!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href = "http://www.cs.wisc.edu/~david/david.html"> David Wood</em><br></td><td align=center valign=top><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#wwt">Tempest: A Substrate for Portable Parallel Programs</a></td></tr><tr><td align=center valign=top>Sep 17</td><td align=center valign=top><em><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href = "http://www.cs.wisc.edu/~sohi/sohi.html"> Guri Sohi</em><br></td><td align=center valign=top><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#sohi">Computing with billion transistor chips</a></td></tr><tr><td align=center valign=top>Sep 24</td><td align=center valign=top><em><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href = "http://www.cs.wisc.edu/~toshi/toshi.html"> Toshiyuki Shimizu</em><br></td><td align=center valign=top><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#toshi">AP3000 Parallel Server</a></td></tr><tr><td align=center valign=top>Oct 1</td><td align=center valign=top><em><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><a href = "http://www.cs.wisc.edu/~glew/glew.html"> Andy Glew</em><br></td><td align=center valign=top><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#glew">Logical Circuit Speed Limits</a></td></tr><tr><td align=center valign=top>Oct 8</td><td align=center valign=top><em>...</em><br></td><td align=center valign=top>...</a></td></tr><tr><td align=center valign=top>Oct 15</td><td align=center valign=top><em><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><a href = "http://www.cs.wisc.edu/~jes/jes.html"> Jim Smith</em><br></td><td align=center valign=top><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#smith">Prediction and Speculation: Current Status and Future Directions</a></td></tr><tr><td align=center valign=top>Oct 22</td><td align=center valign=top><em>...</em><br></td><td align=center valign=top>...</a></td></tr><tr><td align=center valign=top>Oct 29</td><td align=center valign=top><em><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><a href = "http://www.cs.wisc.edu/~austin/austin.html"> Todd Austin</em><br></td><td align=center valign=top>Microprocessor Research Challenges</a></td></tr><tr><td align=center valign=top>Nov 5</td><td align=center valign=top><em><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><a href = "http://www.cs.wisc.edu/~ericro/ericro.html"> Eric Rotenberg</em><br></td><td align=center valign=top><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#rotenberg">Assigning Confidence to Conditional Branch Predictions</a></td></tr><tr><td align=center valign=top>Nov 12</td><td align=center valign=top><em><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><a href = "http://www.cs.wisc.edu/~alain/alain.html"> Alain Kagi</em><br></td><td align=center valign=top>TBA</a></td></tr><tr><td align=center valign=top>Nov 18</td><td align=center valign=top><em>Dan Scales</em><br></td><td align=center valign=top><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><a href = "http://www.cs.wisc.edu/~arch/uwarch/abstracts_f96.html#scales">Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory</a></td></tr><tr><td align=center valign=top>Nov 19</td><td align=center valign=top><em><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><a href = "http://www.cs.wisc.edu/~schoinas/schoinas.html"> Ioannis Schoinas</em><br></td><td align=center valign=top>TBA</a></td></tr><tr><td align=center valign=top>Nov 26</td><td align=center valign=top><em><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><a href = "http://www.cs.wisc.edu/~subbarao/subbarao.html"> Subbarao Palacharla</em><br></td><td align=center valign=top>TBA</a></td></tr><tr><td align=center valign=top>Dec 3</td><td align=center valign=top><em>MICRO ??</em><br></td><td align=center valign=top>...</a></td></tr><tr><td align=center valign=top>Dec 10</td><td align=center valign=top><em><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><a href = "http://www.cs.wisc.edu/~dburger/dburger.html"> Doug Burger</em><br></td><td align=center valign=top>Design Issues for Future On-Chip Memory Hierarchies</a></td></tr><tr><td align=center valign=top>Dec 17</td><td align=center valign=top><em><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><a href = "http://www.cs.wisc.edu/~kaxiras/kaxiras.html">  Stefanos Kaxiras</em><br></td><td align=center valign=top>...</a></td></tr></table></center>TBA = To Be Announced<br><br><p><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><a href = "http://www.engr.wisc.edu/~gubner/ece600/schedule.html">ECE Architecture Seminars</a></body><br> <hr><ADDRESS>This page was created by <!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><A HREF="http://www.cs.wisc.edu/~vijay">T.N. Vijaykumar</a>, University of Wisconsin-Madison <!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><A HREF="http://www.cs.wisc.edu/">Computer Sciences Department</a>.<p>Last modified by <I><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><A HREF="http://www.cs.wisc.edu/cgi-bin/finger?vijay">vijay@cs.wisc.edu</A><BR>Tue Sep 3 10:30:53 CST 1996</I></ADDRESS></html>
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