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Date: Tue, 05 Nov 1996 00:32:49 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Wed, 30 Aug 1995 21:21:35 GMTContent-length: 20185<html><head><title> Lecture notes - Chapter 14 - Architectures</title></head><BODY><h1> Chapter 14 -- Architectures</h1><pre>PERSPECTIVE ON ARCHITECTURE DESIGN----------------------------------factors in computer design: speed as fast as possible, of course dependent on technology and cost cost/price profit, non-profit, mass market, single use useablility shared/single user, size of machine, OS/software issues, power requirements depends on intended use! intended market mass market, scientific research, home use, multiple users, instructional, application specific technologyprice/performance curve ^ | perf. | | x | x Want to be to the "left" of these, | x to have higher performance for the | price. "More bang for the buck." | x x _________________ price -> technology -- a perspective---------- electromechanical (1930) -- used mechanical relays vacuum tubes (1945) space requirement: room Manchester Mark 1 (late 1940s) transistors discrete (late 1950s) space requirement: a large cabinet to a room Examples: CDC 6600 B 5000 Atlas (?) PDP 11/10 SSI, MSI (mid-late 1960s) 1-10 10-100 transistors space requirement: a cabinet Examples: Cray 1 VAX 11/780 LSI (early 1970s) 100-10,000 transistors space requirement: a board Examples: VLSI (late 1970s - today) >10,000 transistors space requirement: a chip, or chip set, board Examples: MIPS R2000 Intel 386 (~275,000 transistors) Sparc RISC vs. CISC------------- RISC - Reduced Instruction Set Computer The term was first used to name a research architecture at Berkeley: the RISC microprocessor. It has come to (loosely) mean a single chip processor that has the following qualities: 1. load/store architecture 2. very few addressing modes 3. simple instructions 4. pipelined implementation 5. small instruction set -- easily decoded instructions 6. fixed-size instructions CISC - Complex Instruction Set Computer This term was coined to distinguish computers that were not RISC. It generally is applied to computers that have the following qualities: 1. complex instructions 2. large instruction set 3. many addressing modesdifficulties with these terms - not precisely defined - term introduced/applied to earlier machines - "RISC" has become a marketing toolsingle chip constraint----------------------As technologies advanced, it became possible to put a processor on a single VLSI chip. Designs became driven by how much (how many transistors) could go on the 1 chip. Why? 1. The time it takes for an electrical signal to cross a chip are significantly less than the time for the signal to get driven off the chip to somewhere else. 2. The number of pins available was limited. So, the desire is to have as little interaction of the chip with the outside world as possible. It cannot be eliminated, but it can be minimized.The earliest of single processors on a chip had to carefullypick and choose what went on the chip. Cutting-edge designstoday can fit everything but main memory on the chip. how the world has changed------------------------- earliest computers had their greatest difficulties in getting the hardware to work -- technology difficulties space requirements cooling requirements given a working computer, scientists would jump through whatever hoops necessary to use it. as hardware has gotten (much) faster and cheaper, attention has been diverted to software. OS compilers optimizers IPC (inter-process communication)1 instruction at a time isn't enough. The technologyisn't "keeping up." So, do more than one instructionat a time:parallelism----------- instruction level (ILP) -- pipelining superscalar -- more than one instruction at a time multis VLIW supercomputer WHICH OF THESE IS "BEST" and "FASTEST" DEPENDS ON WHAT PROGRAM IS BEING RUN -- THE INTENDED USEAGE. on the 68000 Family--------------------- released in the late 1970's- an early "processor on a chip"- a lot of its limitations have to do with what could fit on a VLSI chip in the late 1970'sINSTRUCTIONS - a relatively simple set (like the MIPS) but NOT a load/store arch. - a two-address architecture - most instructions are specified in 16 bits -- fixed size. - tight encoding, it is difficult to distinguish opcode from operands, but the m.s. 4 bits are always part of the opcode. integer arithmetic different opcode for varying size data (add.b add.w add.l) logical different opcode for varying size data control instructions conditional branches, jumps (condition code mechanism used -- where most instructions had the effect of setting the condition codes) procedure mechanisms call and return instructions floating point ?? (I guess not!) decimal string arithmetic presuming representation of binary coded decimalREGISTERS 16 32-bit general purpose registers, only one is not general purpose (it is a stack pointer) the PC is not part of the general purpose registers the registers are divided up into two register files of 8, one is called the D (data) registers, and the other is called the A (address) registers. This is a distinction similar to the CRAY 1. A7 is the stack pointer. DATA TYPES byte word (16 bits) longword (32 bits) addresses are really their own data type. arithmetic on A registers is 32 bit arithmetic. However, pin limitations on the VLSI chip required a reduced size of address. Addresses that travel on/off chip are 24 bits -- and the memory is byte-addressable. So a 24-bit address specifies one of 16Mbyte memory locations.each instruction operates on a fixed data typeOPERAND ACCESS the number of operands for each individual instructions is fixed like the VAX, the addressing mode of an operand does not depend on the instruction. To simplify things, one of the operands (of a 2 operand instruction) must usually come from the registers. the number/type of addressing modes is much larger than the MIPS, but fewer than the VAX. the text has a detailed discussion of the 68000 addressing modes. READ IT!PERFORMANCE ?, they got faster as new technologies got faster.SIZE 1 64-pin VLSI chip (a huge number of pins at that time) the Intel iAPX 86-----------------the 8086 - late 1970's release - a one- or two- address architecture (depending on how you look at it) - part of a chip set pin limitations on the chips made for some unusual architectural design decisions. - compatible with earlier 8085 chip set a memory-to-memory architecture, sort of 3 16-bit registers, plus an accumulator, a stack pointer, and a PC (plus 4 more that deal with segments) condition codes are set by most instructions,and are used in branching an unusual addressing scheme: (due to a 16-bit limitation for pins used for addresses) divide all of memory into fixed-size, 64K byte pieces call each piece a segment. addresses are 16 bits, and specify an offset within one of the segments 4 extra registers hold segment base addresses, and an effective address is computed (sort of) by 1. specifying which segment register 2. adding the 16-bit address to the contents of the segment register this addressing scheme "cramps a programmer's style". code has to fit into a segment -- so does data, and so does a stack. all about the Cray 1-------------------- There has always been a drive to design the best, fastest computer in the world. Whatever computer is the fastest has generally been called a supercomputer. The Cray 1 earned this honor, and was the fastest for a relatively long period of time. The man who designed the machine, Semour Cray, is a bit of an eccentric, but he can get away with it because he's so good. The Cray 1 has an exceptionally "clean" design, and that makes it fast. (This is probably a bit exaggerated due to my bias -- the Cray 1 is probably my favorite computer.) Mostly my opinion: To make the circuitry as fast as possible, the Cray 1 took 2 paths 1. Physical -- a relatively "time-tested" technology was used, but much attention was paid to making circuits physically close (Semour was aware of the limits imposed by the speed of light.)⌨️ 快捷键说明
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