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Date: Tue, 05 Nov 1996 22:01:56 GMTServer: NCSA/1.5Content-type: text/htmlLast-modified: Tue, 18 Jun 1996 15:55:21 GMTContent-length: 1737<html><head><title> Course Projects </title></head><body><base href="http://www.cs.wisc.edu/~dburger/"><h3> Course Projects</h3><hr><ul><strong><li> CS/ChE 838-3</strong><br>Translated Appbt, one of the NAS Parallel Benchmarks, from FORTRANto C and parallelized it for use on a shared-memory multiprocessor.It was ported to the Wisconsin Wind Tunnel for use as a researchbenchmark.<p><strong><li> CS/ECE 757</strong><br>Studied the effect of limited broadcast cache-coherence protocolson invalidation traffic in highly parallel shared-memory multiprocessors.Our measurements were obtained with the Wisconsin Wind Tunnel.<p><strong><li> CS/ECE 755</strong><br>Designed JIHAD, a ~5500 transistor VLSI DRAM controller, to be usedin a proposed RamLink memory system. The chip was fabricated andunderwent successful testing (i.e., it worked).<p><strong><li> CS/ECE 752</strong><br>Designed and simulated (gate-level) CORDIC hardware to approximatetrigonometric functions in IEEE floating point format.<p><strong><li> CS 747</strong><br>Developed a queueing model to represent a large-scale shared memorymultiprocessor, using homogenous processing nodes and a constant delaymodel.<p><strong><li> CS 736</strong><br>Modified the Wisconsin Wind Tunnel to support simulation of virtualmemory and demand paging, to study paging behavior of parallelscientific codes on shared-memory multiprocessors. <p><strong><li> CS 701</strong><br>Wrote a compiler for ADA/CS, a subset of the ADA programming language.The target assembler code was a variant of MIPS.<p><strong><li>CS/ECE 552</strong><br>Designed and simulated (gate-level) a simple RISC CPU in the Galaxy programming environment.<p></ul></body></html>⌨️ 快捷键说明
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