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Business Machines Inc., and Motorola Inc.
<li><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><!WA227><a href="http://mkp.com/pages/2704/index.html">The Designer's Guide to
VHDL</a> by Peter J. Ashenden
<li><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><!WA228><a href="http://www.bh.com/dp/55558130.htm">Alpha Implementations and Architecture</a> by Dileep P. Bhandarkar
<li><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><!WA229><a href="http://mkp.com/pages/2976/index.html">The MIPS Programmer's
Handbook</a> by Erin Farquhar and Philip Bunce
<li><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><!WA230><a href="http://umunhum.stanford.edu/book.html">Computer Architecture: Pipelined and Parallel Processor Design</a> by Michael J. Flynn
<li><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><!WA231><a href="http://www.apcatalog.com/cgi-bin/AP?ISBN=0123229855&LOCATION=US&FORM=FORM2">The Cache Memory Book</a> by Jim Handy
<li><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><!WA232><a href="http://mkp.com/pages/3298/index.html">Computer Architecture: A
Quantitative Approach, Second Edition</a> by John L. Hennessy and David A.
Patterson
<li><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><!WA233><a href="http://mkp.com/pages/3166/index.html">The PowerPC Architecture: A
Specification for a New Family of RISC Processors</a> by International
Business Machines Inc. 
<li><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><!WA234><a href="http://mkp.com/pages/3441/index.html">RISC System/6000: PowerPC
System Architecture</a> by International Business Machines Inc.
<li><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><!WA235><a href="http://www.ecs.umass.edu/ece/koren/arith">Computer Arithmetic Algorithms</a> by Israel Koren
<li><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><!WA236><a href="http://mkp.com/pages/1171/index.html">Introduction to Parallel
Algorithms and Architectures: Arrays, Trees, and Hypercubes</a> by F.
Thomson Leighton
<li><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><!WA237><a href="http://mkp.com/pages/3158/index.html">Scalable Shared-Memory
Multiprocessing</a> by Daniel E. Lenoski and Wolf-Dietrich Weber
<li><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><!WA238><a href="http://mkp.com/2542/index.html">Parallel Processing from
Applications to Systems</a> by Dan I. Moldovan
<li><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><!WA239><a href="http://mkp.com/pages/281X/index.html">Computer Organization and
Design: The Hardware/Software Interface</a> by David A. Patterson and John
L. Hennessy
<li><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><!WA240><a href="http://mkp.com/pages/1368/index.html">Cache and Memory Hierarchy
Design: A Performance-Directed Approach</a> by Steven A. Przybylski
<li><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><!WA241><a href="http://mkp.com/pages/3791/index.html">The DLX Instruction Set
Architecture Handbook</a> by Philip M. Sailer and David R. Kaeli
<li><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><!WA242><a href="http://www.cs.cmu.edu/~koopman/titan/index.html">The Architecture of Supercomputers: Titan, a case study</a> by Daniel Siewiorek and Philip Koopman
<li><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><!WA243><a href="http://www.shore.net/~ws/COA4e.html">Computer Organization and Architecture, Fourth Edition</a> by William Stallings
<li><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><!WA244><a href="http://mkp.com/pages/2798/index.html">POWER and PowerPC:
Principles, Architecture, Implementation</a> by Shlomo Weiss and James E. Smith
</ul>
<hr>
<h2><A NAME="Publications">Architecture-related on-line publication resources</a></h2>
<h3>Bibliographies</h3>
<ul>
<li><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><!WA245><A HREF="http://www-acaps.cs.mcgill.ca/doc/">Architecture bibtex bibliographies</A>
<li><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><!WA246><A HREF="http://www.cs.wisc.edu/~arch/www/ISCAbib/isca_bib.html">ISCA Bibliographies </a>
</ul>
<h3>Bibliographies</h3>
<ul>
<li><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><!WA247><A HREF="http://www-acaps.cs.mcgill.ca/doc/">Architecture bibtex bibliographies</A>
<li><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><!WA248><A HREF="http://www.computer.org/pubs/tpds/tpds.htm">IEEE Transactions on Parallel and Distributed Systems</a>
<li><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><!WA249><A HREF="http://www.cs.wisc.edu/~arch/www/ISCAbib/isca_bib.html">ISCA Bibliographies </a>
</ul>
<h3>Conference proceedings</h3>
<b>1996</b><br>
<ul>
<li><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><!WA250><A HREF="http://cag-www.lcs.mit.edu/asplos7/program/">ASPLOS VII</a>
</ul>
<b>1995</b><br>
<ul>
<li><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><!WA251><A HREF="http://american.cs.ucdavis.edu/Micro28/html/finalprogram.html">Micro-28</a>
<li><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><!WA252><A HREF="http://www.supercomp.org/sc95/proceedings/">Supercomputing '95</a>
</ul>
<b>1994</b><br>
<ul>
<li><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><!WA253><A HREF="http://american.cs.ucdavis.edu/Micro27/html/finalprogram.html">Micro-27</a>
<li><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><!WA254><A HREF="http://www.computer.org/conferen/sc94/sctoc.html">Supercomputing '94</a>
</ul>
<hr>
<h2><A NAME="Miscellanea">Miscellanea</A> </h2>
<ul>
<li><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><!WA255><A HREF="http://www.csrd.uiuc.edu/iacoma/augmint">Augmint tracing-simulation tool</A>
<li><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><!WA256><A HREF="http://hpwww.epfl.ch/bench/bench.FAQ.html">Benchmarks FAQ</A>
<li><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><!WA257><A HREF="ftp://ee.byu.edu/BACH/">BYU Trace Archive</A>
<li><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><!WA258><A HREF="http://einstein.et.tudelft.nl/~offerman/chiplist.html">Chip List for IBM PCs and Compatibles</A>
<li><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><!WA259><A HREF="http://www.cs.cmu.edu/afs/cs/project/multiC-sys-sw/WWW/top.html">CMU Multicomputer System Software</A>
<li><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><!WA260><A HREF="http://www.acs.oakland.edu/~awesley/pipetop.htm">Computer Pipelining: An overview with historical background</a>
<li><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><!WA261><A HREF="http://infopad.eecs.berkeley.edu/CIC/">CPU Info Center</a> (UC-Berkeley)
<li><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><!WA262><A HREf="http://www.cera.com/faqroad.htm">FAQ Roadmap: Embedded Systems Internet</A>
<li><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><!WA263><A HREF="http://www.cs.umd.edu/users/fms/comp/">Historical Computers</a> (University of Maryland) 
<!-- www.nvg.unit.no in autumn <br> -->
<li><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><!WA264><A HREF="http://www.cs.washington.edu/homes/pardo/sim.d/index1.d/Index.html">Instruction Set Simulation and Tracing Tools</a>
<li><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><!WA265><A HREF="http://www.intel.