http:^^www.cs.washington.edu^homes^tullsen^research.html

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Date: Tue, 10 Dec 1996 21:56:31 GMTServer: NCSA/1.4.2Content-type: text/htmlLast-modified: Tue, 27 Feb 1996 19:42:38 GMTContent-length: 1621<title> Research Interests </title>  <BODY            BACKGROUND="http://home.netscape.com/home/bg/rock/gray_rock.gif"            TEXT="#D1FF00"            LINK="#00F4FF"            VLINK="#00FF2E"><h1> Dean Tullsen's Research Interests </h1>Computer architecture, caches, superscalar processors, multithreadedprocessors, superscalar multithreaded processors ...<h2> Bibliography </h2>D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm, <A HREF = "ISCA96.ps">Exploiting Choice:  Instruction Fetch and Issue on anImplementable Simultaneous Multithreading Processor</A>, In 23rd Annual International Symposium on Computer Architecture, May, 1996(see <A HREF = "ISCA96abstract.html">abstract</a>)<P>D.M. Tullsen, S.J. Eggers, and H.M. Levy, <A HREF = "ISCA95.ps">SimultaneousMultithreading:   Maximizing On-Chip Parallelism</A>, In 22nd Annual International Symposium on Computer Architecture, June, 1995(see <A HREF = "ISCA95abstract.html">abstract</a>)<P>D.M. Tullsen, S.J. Eggers, <A HREF = "ACMTOCS.ps">Effective CachePrefetching on Bus-Based Multiprocessors</A>, ACM Transactionson Computer Systems, pp. 57-88, February, 1995(see <A HREF = "TOCSabstract.html">abstract</a>)<P>D.M. Tullsen, S.J. Eggers, <A HREF = "ISCA93.ps">Limitations of Cache Prefetching on a Bus-Based Multiprocessor</A>, In 20th Annual International Symposium on Computer Architecture, pp 278-288,1993(see <A HREF = "ISCA93abstract.html">abstract</a>)<P>D.M. Tullsen, M.D. Ercegovac, Design and VLSI Implementation of anOnline Algorithm, Real Time Signal Processing IX, August, 1988

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