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Date: Mon, 02 Dec 1996 15:11:36 GMTServer: NCSA/1.4.2Content-type: text/html<HTML><head><title>CSE467 Schedule</title></head><body bgcolor="#dddddd" text="#000000" link="#0000ee" vlink="501080" alink="ff0000"><h1>CSE467: Advanced Logic Design</h1><h3>Carl Ebeling, Spring 1996 </h3><hr><h3>List of topics and concepts covered this quarter:</h3><UL><LI> Truth tables and structured logic implementations<LI> PAL architectures and implementation issues<LI> PROM implementation of functions<LI> PLAs<LI> Multiplexors for functions<LI> Decoders and large decoder structures<LI> Tristate logic for multiplexing and busses<LI> TTL and CMOS logic families and interfacing issues<LI> Voltage levels and noise margins<LI> Current sink and drive capabilities of logic families<LI> Mixed logic notation, deMorgan's law<LI> Synchronous circuit design methodologies<LI> Timing characteristics of registers: setup/hold constraints and propagation delays<LI> Effects of clock skew<LI> Asynchronous inputs, "synchronizers" and metastability problems<LI> Finite state machine models: Mealy vs. Moore machines<LI> State diagrams and compiling to state tables and circuit implementation<LI> PLD implementation of state machines<LI> FGPA architectures: logic blocks and routing structures<LI> FPGA design methodologies and CAD tools: place and route<LI> 2-level logic minimization<LI> Multi-output function minimization<LI> Multilevel logic synthesis<LI> Algebraic and boolean division, kernel and cube factors<LI> Logic transformations including factoring and Shannon decomposition<LI> Techniques for mapping complex functions to PLDs<LI> Memory structures and control<LI> Static RAM architecture and timing<LI> Dynamic RAM architecture and timing<LI> Serial communication<LI> ABEL programming<LI> Oscilloscopes and Logic Analyzers</UL></body><address><hr>ebeling@cs.washington.edu</address><p></html>⌨️ 快捷键说明
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