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Date: Mon, 02 Dec 1996 15:13:14 GMTServer: NCSA/1.4.2Content-type: text/html<HTML><head><title>CSE567 Summary</title></head><body bgcolor="#ffffff" text="#000000" link="#0000ee" vlink="501080" alink="ff0000"><h1>CSE 567: Principles of Digital Systems Design</h1><h3>Carl Ebeling, Fall 1996 </h3><hr><b>Catalog Data</b>: Principles of logic design, combinational andsequential circuits, structured design methods, digital systemcomponents, clocking methodologies, arithmetic circuits, memories,hardware description languages, logic and sequential synthesis,synthesis and simulation tools, implementation alternative, VLSIprocessor architecture, application-specific computation.<p><b>Prerequisites</b>:A working knowledge of Boolean algebra and finite-state machines.<BR>Familiarity with the department's computing environment: Unix/X<p><b>Course Goals</b>:To provide in-depth understanding of digital systems and their design, including specification, synthesis, and implementation.<p><b>Facilities</b>:You will be making extensive use of computer-aided design (CAD) toolsfor designing and implementing digital circuits. These tools areinstalled on the Sun workstations of the Northwest Laboratory forIntegrated Systems (LIS). These are (mostly) located in Sieg 424 butare accessible from any X-terminal. You may find it advantageous towork in 424 where you can take advantage of manuals, reference textsand the knowledge of other students.<p> <b>CAD Tools</b>: CAD tools allow us to design and implementsubstantial hardware projects in a reasonable amount of time. Theyalso provide hands-on experience with state-of-the-art design toolsthat incorporate the synthesis algorithms covered in class. Thesetools are introduced during the first half of the course as basicconcepts are covered and then used heavily for the design project.<UL><li> <b>Verilog:</b> Verilog is a text-based hardware description language which allows both structural and behavioral descriptions. This course concentrates on structural design but introduces behavioral descriptions and synthesis. Cadence tools are used to simulate the Verilog descriptions.<!-- \item {\bf Xdp and WireC} Xdp is an X-windows based drawing program that is used in conjunction with WireC to produce circuit schematics. This courses uses Xdp/WireC to allow students to draw schematics which in turn are compiled directly into structural Verilog.--><li> <b> Synopsys</b> The Synopsys synthesis tools are used to synthesize implementations from the Verilog descriptions. This course uses Synopsys to investigate the synthesis process as well as a ``turn-key'' synthesis for implementing the final project.</UL><p><b>Assignments</b>: There will be weekly assignments and labs duringthe first half of the quarter. They will give you experience withthe concepts you will be using in the second half of the quarter forthe design project and introduce you to the CAD tools.<p><b>Project</b>: A substantial part of the course revolves around theteam design of a large hardware systems project. Each team willdesign a complete project using schematics and Verilog forspecification, Verilog-XL for simulation, the Synopsys tools forsynthesis, and Xilinx FPGAs for implementation. Design projects inthe past have included a Tetris player, an Ethernet interface, a cachemonitor and DNA sequence matching. This quarter we will be designinghardware to implement an image processing algorithm. I haven'tdecided which algorithm yet, but examples include compression, filtering, edge detection, etc. We will be using aprototyping board containing several FPGAs and RAM that plugs into anAlpha workstation via a PCI bus. An image will be downloaded into theon-board RAM, transformed by the hardware into a compressed orfiltered image, and then uploaded to the Alpha. The project will bewell-defined, but students will be able to explore different optionsbased on performance or cost as well as other possibilities such ascolor images or video.<p><b>Collaborative Learning</b>:It is well known that students can learn a lot from each other giventhe chance. During the second week I will assign everyone into teamsof three and four students. You will work together on the homeworkassignments and the project. Each member of the team will beresponsible for the performance of all other team members; that is,the entire team must understand the solution and contribute to part ofit. We will talk about how this works in more detail later.<p><b>Quizzes and Exams</b>:There will be a short but challenging quiz every Friday at the end ofclass which will cover all material covered through that Wednesday.As compensation, there will be no mid-term exam. The final exam willbe a two-hour comprehensive examination given at the regularlyscheduled final exam time. Quizzes and the final exam will be openbook and open notes.<p><b>Grading</b>:The course grade will be roughly determined as follows:<ul> <li>Assignments (homework and laboratory): 20% <li>Quizzes: 20% <li>Project: 40% <li>Final Exam: 20% <li>Participation and intangibles: 10%</ul></body><address><hr>ebeling@cs.washington.edu</address><p></html>⌨️ 快捷键说明
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