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Date: Mon, 02 Dec 1996 14:51:11 GMTServer: NCSA/1.4.2Content-type: text/html<html><head><title>CSE471 --- Computer Design and Organization</title></head><h1> <a name="top">CSE471 --- Computer Design and Organization</a><br></h1><hr><h2> General Information <br> </h2>Meets: MWF 10:30-11:20, Loew 106 <br>Instructor: Ted Kehl <br>Office Hours: Wednesday 2-3, Thursday 11.30-12.30<br>E-mail address: ted@cs <br>Office: Sieg 211 543-2421 <br><p>TA: Meng-Hee Heng <br>Office Hour: Mon 3.00-4.30, Thur 1.30-3.00 Sieg 326A<br>E-mail address: menghee@cs <br><br><hr><h2> Catalog Description <br></h2>CPU instruction addressing models, CPU structure and functions,computer arithmetic and logic unit, register transfer level design,hardware and microprogram control, memory hierarchy design andorganization, I/O and system components interconnection. Laboratoryproject involves design and simulation of an instruction setprocessor. <p>Prerequisite: CSE 370 and CSE 378. <p><hr><h2> Class notes </h2><a href="day01n.ps"> Day 1 (Postscript) </a> <br><a href="day02n.ps"> Day 2 (Postscript) </a> <br> <a href="day04n.ps"> Day 4 (Postscript) </a> <br><a href="day05n.ps"> Day 5 (Postscript) </a> <br><a href="day06n.ps"> Day 6 (Postscript) </a> <br><a href="day08n.ps"> Day 8 (Postscript) </a> <br><a href="day09n.ps"> Day 9 (Postscript) </a> <br><a href="day10n.ps"> Day 10 (Postscript) </a> <br><a href="day13n.ps"> Day 13 (Postscript) </a> <br><a href="day16n.ps"> Day 16 (Postscript) </a> <br><a href="day19n.ps"> Day 19 (Postscript) </a> <br><a href="day25n.ps"> Day 25 (Postscript) </a> <br><a href="day30n.ps"> Day 30 (Postscript) </a> <br><p><hr><h2> Previous Quarters </h2> <a href="A94_index.html> Fall 94 </a><p><hr><h2>Verilog References</h2>This is a free Postscript<a href="ref.ps"> Verilog reference card. </a><p><hr>Meng-Hee Heng<br><i> menghee@cs.washington.edu</i></html>⌨️ 快捷键说明
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