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<!doctype html public "-//W30//DTD W3 HTML 2.0//EN"><HTML><TITLE>CONCURRENT VLSI ARCHITECTURE GROUP</TITLE><center><!WA0><A HREF="http://www.ai.mit.edu/projects/cva/cva_home_page.html"><!WA1><IMG SRC=http://www.lcs.mit.edu/web_project/Brochure/cva/cvaline.gif></a></center><p><center><table border><tr> <td><!WA2><img src=http://www.lcs.mit.edu/web_project/Brochure/cva/dally.gif></td></tr><tr><td> <!WA3><a href="http://www.ai.mit.edu/people/billd/billd.html"><address><b>William J. Dally</b></a>,<br>Associate Professor <br>of Computer Science and Engineering</address></tr></table></center><body><p>Much of the work of the Concurrent VLSI Architecture groupis experimental in nature: We build working chips,machines, and programs to test new concepts and gaininsight in applying VLSI technology to informationprocessing. As illustrated by the following examples, ourprojects address parallel computer architecture andsoftware, interconnection networks, special-purposeprocessor design, and VLSI design.<p>The <!WA4><A HREF="http://www.ai.mit.edu/projects/cva/cva_m_machine.html">M-Machine</a> is a multicomputer that will test newconcepts for controlling multiple function units on asingle chip, efficient and flexible communicationprimitives, fine-grain protection, and global memorysystems. The project seeks out methods for exploitinginstruction-level parallelism within a task and amongtasks, on the same node and between multiple nodes.<p>The M-Machine consists of up to 64K nodes connected by ahigh-speed 3-D mesh network. Each node includes a multi-ALUprocessor (MAP) chip and external memory. A MAP chipcontains 12 arithmetic units, memory management hardware,and a network interface. The chip's target performance is800 megaFLOPS.<p>Atomic SEND instructions provide efficient communication bytransmitting a message out of registers. Messages areremoved from the network and dispatched by programmablesoftware handlers. The memory-system architecture providesa global virtual address space in which addresses may betranslated into local or remote physical locations. Synchronization is provided via tags on memory words. Theaddress spaces of individual threads are separated andprotected using segments and privileged access pointers.<p>Our software research seeks to advance the state of the artin transforming a sequential application to an efficientparallel version. Such transformations (which are now verylabor-intensive) should be smooth and painless. Ourcompiler will employ both user directives and automaticanalyses to provide users with precisely the control thatis needed at each stage of the transformation. Thiscombination will allow users to focus first on algorithmicconcerns, leaving optimization to the compiler. Users maythen specify directives to improve performance for the fewcritical aspects of the program, possibly using informationnot available to the compiler.<p>The <!WA5><A HREF="http://www.ai.mit.edu/projects/cva/cva_router.html">Reliable Router</a> is a high-speed, fault-tolerant 2-Dmesh router VLSI chip for use in massively parallelprocessors; we plan to use the router in parallel computersand in network switching hubs. Features include networkfault tolerance via a link-level retry, plesiochronoustiming to avoid the need for a global clock, adaptiverouting for fault and congestion avoidance, virtualchannels for performance under heavy load, support forrequest/reply protocols, and random/deadline arbitrationschemes for livelock avoidance. Electrical interconnectbetween routers uses simultaneous bidirectional signaling.Bandwidth per port is 400Mb/sec at a chip clock rate of100MHz.</BODY><p><!WA6><a href="http://www.lcs.mit.edu/web_project/Brochure/contents.html"><!WA7><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/contents_motif.gif></a><!WA8><a href="http://www.lcs.mit.edu/web_project/Brochure/cdm/cdm.html"><!WA9><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/previous_group_motif.gif></a><!WA10><a href="http://www.lcs.mit.edu/web_project/Brochure/cag/cag.html"><!WA11><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/next_group_motif.gif></a></HTML>⌨️ 快捷键说明
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