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Date: Mon, 25 Nov 1996 23:58:23 GMT
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<TITLE>Rocket</TITLE><BODY BACKGROUND="gray.gif" link="red" vlink="maroon"><!WA0><img src="http://www.cs.mtu.edu/~carr/Bluebar.gif"><H1> The Rocket Project </H1><H2> Principal Investigators: </H2><UL><LI> <!WA1><A HREF="http://www.cs.mtu.edu/faculty/Sweany.html">Philip H. Sweany</A><LI><!WA2><A HREF="http://www.cs.mtu.edu/~carr">Steve Carr</A></UL><P><H2>Current Graduate Students:</H2><UL><LI><!WA3><A HREF="http://www.cs.mtu.edu/grads/Ding.html">Chen Ding</A><LI> <!WA4><A HREF="http://www.cs.mtu.edu/grads/Jang/Home.html">Saurabh Jang</A><LI><!WA5><A HREF="http://www.cs.mtu.edu/grads/Schemm.html">Evan L. Schemm</A><LI> <!WA6><A HREF="http://www.cs.mtu.edu/grads/Suchyta.html">Thomas R. Suchyta</A><LI><!WA7><A HREF="http://www.cs.mtu.edu/grads/Wu.html">Qunyan Wu</A></UL><H2>Current Undergraduates:</H2><UL><LI>Denise Junker<LI>Denise Wieber</UL><H3>Description:</H3><P>The goals of the Rocket project are to develop a retargetable compiler forinstruction-level parallel architectures and to develop scheduling and register allocationalgorithms for said architectures.  This project intimatelyis entwined with the <!WA8><A HREF="http://www.cs.mtu.edu/~carr/Memoria.html">Memoria</A> project. Current research effortsinclude software pipelining, register-sensitive scheduling, and register allocation andscheduling for partitioned register files.<P><STRONG> Publications:</STRONG><P>S. J. Beaty, S. Colcord, P.H. Sweany.<!WA9><A HREF="ftp://cs.mtu.edu/pub/sweany/heuristicGA.ps">"Using Genetic Algorithms to Fine-Tune Instruction-Scheduling Heuristics"</A>,In Proceedings of MCPS '96.<P>M.J. Bourke III, P.H. Sweany, S.J. Beaty.<!WA10><A HREF="ftp://cs.mtu.edu/pub/sweany/FBLS.ps">"Extending List Scheduling to Consider Execution Frequency"</A>,In Proceedings of the 29th Annual Hawaii International Conference on System Sciences.<P>S. Carr, C. Ding and P. Sweany</A>,<!WA11><A HREF="ftp://cs.mtu.edu/pub/carr/softpipe.ps.gz">"Improving Software Pipelining with Unroll-and-Jam"</A>, In Proceedings of the 29th Annual Hawaii International Conference on System Sciences. <P>T. Brasier, P. Sweany</A>, S. Beaty andS. Carr, <!WA12><A HREF="ftp://cs.mtu.edu/pub/carr/craig.ps.gz">"CRAIG: A Practical Frameworkfor Combining Instruction Scheduling and Register Assignment"</A>, 1995 InternationalConference on Parallel Architectures and Compiler Techniques. <P>P.H. Sweany, S.J. Beaty.<!WA13><A HREF="ftp://cs.mtu.edu/pub/sweany/micro25.ps">"Dominator-Path Scheduling: A Global Scheduling Method"</A>,Proceedings of the 25th International Symposium on Microarchitecture (MICRO-25).<P>P.H. Sweany, S.J. Beaty.<!WA14><A HREF="ftp://cs.mtu.edu/pub/sweany/micro23.ps">"Post-Compaction Register Assignment in a Retargetable Compiler"</A>,In Proceedings of the 23rd Microprogramming Workshop (MICRO-23).<P><STRONG> Research Grants:</STRONG><P>"Generating Efficient Code for Horizontal Micro-Architectures With Partitioned Register Files", Texas Instruments, 1995-1996, $23,715.<P>"Hiding the Latency Between Level-1 and Level-2 Cache on the Alpha 21164", Digital Equipment Corporation, 1995-1997,$83,500. <P><STRONG>Masters' Theses:</STRONG><P>M.J. Bourke. <!WA15><A HREF="ftp://cs.mtu.edu/pub/sweany/bourke.thesis.ps">"Frequency-Based List Scheduling: List Scheduling to Incorporate Frequency Information"</A>,Michigan Technological University, Department of Computer Science, May 1993.<P>T.S. Brasier. <!WA16><A HREF="ftp://cs.mtu.edu/pub/sweany/brasier.thesis.ps">"FRIGG: A New Approach to Combining Register Assignment and Instruction Scheduling"</A>,Michigan Technological University, Department of Computer Science, August 1994.<P>B.L. Huber. <!WA17><A HREF="ftp://cs.mtu.edu/pub/sweany/huber.thesis.ps">"Path-Selection Heuristics for Dominator-Path Scheduling"</A>,Michigan Technological University, Department of Computer Science, October 1995.<P>C. Ding. <!WA18><A HREF="ftp://cs.mtu.edu/pub/sweany/ding.thesis.ps">"Improving Software Pipelining with Unroll-and-Jam and Memory-Reuse Analysis"</A>,Michigan Technological University, Department of Computer Science, June 1996.<P>Q. Wu. <!WA19><A HREF="ftp://cs.mtu.edu/pub/carr/qwu.thesis.ps.gz">"Register Allocation via Hierarchical Graph Coloring"</A>,Michigan Technological University, Department of Computer Science, August 1996.
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