http:^^www.cs.mtu.edu^~carr^memoria.html

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Date: Mon, 25 Nov 1996 23:58:31 GMT
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<TITLE>Memoria</TITLE><BODY BACKGROUND="gray.gif" link="red" vlink="maroon"><!WA0><img src="http://www.cs.mtu.edu/~carr/Bluebar.gif"><H1> The Memoria Project </H1><H2>Principal Investigators:</H2><UL><LI><!WA1><A HREF="http://www.cs.mtu.edu/~carr">Steve Carr</A><LI><!WA2><A HREF="http://www.cs.mtu.edu/faculty/Sweany.html">Philip H. Sweany</A></UL><H2>Current Graduate Students:</H2><UL><LI>Raelyn Crowell<LI><!WA3><A HREF="http://www.cs.mtu.edu/grads/Ding.html">Chen Ding</A><LI><!WA4><A HREF="http://www.cs.mtu.edu/grads/Wu.html">Qunyan Wu</A></UL> <H2>Current Undergraduate Students:</H2><UL><LI><!WA5><A HREF="http://colossus.csl.mtu.edu/~djdarlin">Don Darling</A><LI>Denise Wieber</UL><H3>Description:</H3><P>The goals of the Memoria project are to use source-level analysis to improve the memoryperformance of advanced microprocessors.  Current research efforts include algorithms forcombining software prefetching and unroll-and-jam, automatic optimization of linear algebra codes, optimizing loop order for cache performance and using high-level analysisin low-level code generation.  This project is intimately entwined with the <!WA6><A HREF="http://www.cs.mtu.edu/~carr/Rocket.html">Rocket</A> project.<P><STRONG> Publications:</STRONG><P>S. Carr, <!WA7><A HREF="ftp://cs.mtu.edu/pub/carr/combining.ps.gz">"Combining Optimization for Cache and Instruction-Level Parallelism"</A>, To appear in PACT '96, Boston, MA.Michigan Technological University, Department of Computer Science, Technical Report TR95-06.<P><!WA8><A HREF="http://www.cs.umass.edu/~mckinley/home.html">K. McKinley</A>, S. Carr and <!WA9><A HREF="http://www.cs.umd.edu/~tseng">C-W. Tseng</A>,<!WA10><A HREF="ftp://cs.mtu.edu/pub/carr/toplas1736.ps.gz">"Improving Data Locality with Loop Transformations"</A>, To appear in ACM Transaction on Programming Languages and Systems.Michigan Technological University,Department of Computer Science, Technical Report TR95-09. <P>S. Carr, C. Ding and P. Sweany</A>,<!WA11><A HREF="ftp://cs.mtu.edu/pub/carr/softpipe.ps.gz">"Improving Software Pipelining with Unroll-and-Jam"</A>, In Proceedings of the 29th Annual Hawaii International Conference on System Sciences. <P>S. Carr and <!WA12><A HREF="http://www.mcs.anl.gov/home/lehoucq/index.html"> R.B. Lehoucq </A>, <!WA13><A HREF="ftp://cs.mtu.edu/pub/carr/qr.ps.gz">"A Compiler Blockable Algorithm for QR Decomposition" </A>,  Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing.<P>S. Carr, <!WA14><A HREF="http://www.cs.umass.edu/~mckinley/home.html"> K. McKinley</A> and <!WA15><A HREF="http://www.cs.umd.edu/~tseng">C-W. Tseng</A>,<!WA16><A HREF="ftp://cs.mtu.edu/pub/carr/cache.ps.gz">"Compiler Optimizations for Improving Data Locality"</A>, Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems.<P>S. Carr and <!WA17><A HREF="http://www.cs.rice.edu/~ken">K. Kennedy</A>, <!WA18><A HREF="ftp://cs.mtu.edu/pub/carr/unroll.ps.gz">"Improving the Ratio of Memory Operations to Floating-Point Operations in Loops"</A>, ACMTransactions on Programming Languages and Systems, November 1994.<P>S. Carr and <!WA19><A HREF="http://www.cs.rice.edu/~ken">K. Kennedy</A>, <!WA20><A HREF="ftp://cs.mtu.edu/pub/carr/scalar.ps.gz">"Scalar Replacement in the Presence of Conditional Control Flow"</A>, Software -- Practice & Experience 24(1), January 1994.<P>S. Carr and<!WA21><A HREF="http://www.cs.rice.edu/~ken"> K. Kennedy</A>, <!WA22><A HREF="ftp://cs.mtu.edu/pub/carr/block.ps.gz">"Compiler Blockability of Numerical Algorithms"</A>, Proceedings of Supercomputing '92.<P>D. Callahan, S. Carr and <!WA23><A HREF="http://www.cs.rice.edu/~ken">K. Kennedy</A>,<!WA24><A HREF="ftp://cs.mtu.edu/pub/carr/reg.ps.gz">"Improving Register Allocation for Subscripted for Subscripted"</A>, Proceedings of the SIGPLAN 1990 Conference on Programming Language Design and Implementation.<P><STRONG> Invited Publications:</STRONG><P>S. Carr and<!WA25><A HREF="http://www.cs.rice.edu/~ken"> K. Kennedy</A>, <!WA26><A HREF="ftp://cs.mtu.edu/pub/carr/complex.ps.gz">"Compiling Scientific Code for Complex Memory Hierarchies"</A>, Proceedings of 24thHawaii International Conference on System Sciences.<P>S. Carr and<!WA27><A HREF="http://www.cs.rice.edu/~ken"> K. Kennedy</A>, <!WA28><A HREF="ftp://cs.mtu.edu/pub/carr/linear.ps.gz">"Blocking Linear Algebra Codes for Memory Hierarchies"</A>, Proceedings of 4th SIAMConference on Parallel Processing for Scientific Computing.<P><STRONG> Technical Reports:</STRONG><P>S. Carr and Q. Wu, <!WA29><A HREF="ftp://cs.mtu.edu/pub/carr/diminish.ps.gz">"Scalar Replacment and the Law of Diminishing Returns"</A>, Michigan Technological University, Department of Computer Science, Technical Report TR96-04. Submitted to theJournal of Programming Languages.<P>S. Carr and <!WA30><A HREF="http://www.mcs.anl.gov/home/lehoucq/index.html"> R.B. Lehoucq </A>,<!WA31><A HREF="ftp://cs.mtu.edu/pub/carr/matrix.ps.gz">"Compiler Blockability of Dense Matrix Factorizations"</A>, Michigan Technological University, Department of Computer Science, Technical Report TR95-08. Submitted toACM Transactions on Mathematical Software.<P>S. Carr and Q. Wu, <!WA32><A HREF="ftp://cs.mtu.edu/pub/carr/Unroll-and-Jam.ps.gz">"An Analysis of Unroll-and-Jam on the HP 715/50"</A>, Michigan Technological University,Department of Computer Science, Technical Report TR95-05. <P>S. Carr and Q. Wu. <!WA33><A HREF="ftp://cs.mtu.edu/pub/carr/LoopPermutation.ps.gz">"An Analysis of Loop Permutation on the HP PA-RISC"</A>, Michigan Technological University,Department of Computer Science, Technical Report TR95-03. <P>S. Carr and Q. Wu, <!WA34><A HREF="ftp://cs.mtu.edu/pub/carr/ScalarReplacement.ps.gz">"The Performance of Scalar Replacement on the HP 715/50"</A>, Michigan Technological University, Department of Computer Science, Technical Report TR95-02. <P><STRONG> Research Grants:</STRONG><P>"Hiding the Latency Between Level-1 and Level-2 Cache on the Alpha 21164", Digital Equipment Corporation, 1995-1997,$83,500. <P>"Improving the Cache Performance of Scientific Applications", NSF CCR-9409341, 1994-1997, $82,584 with $109,899 in matching funds. <P>"Improving the Memory Performance of the HP PA-RISC", Hewlett-Packard Company, 1994-1995, $56,000. <P>"Cache-Conscious Loop Unrollilng", Hewlett-Packard Company, 1993, $41,000. <P><STRONG> PhD Dissertations:</STRONG><P>S. Carr. <!WA35><A HREF="ftp://cs.mtu.edu/pub/carr/thesis.ps.gz">"Memory Hierarchy Management" </A>,Rice University, Department of Computer Science, September 1992. <P><STRONG>Masters' Theses:</STRONG><P>Y. Guan. <!WA36><A HREF="ftp://cs.mtu.edu/pub/carr/guan.thesis.ps.gz">"Unroll-and-Jam Guided by a Linear-Algebra-Based Memory-Reuse Model"</A>, Michigan Technological University, Department of Computer Science, December 1995.<P>C. Ding. <!WA37><A HREF="ftp://cs.mtu.edu/pub/sweany/ding.thesis.ps">"Improving Software Pipelining with Unroll-and-Jam and Memory-Reuse Analysis"</A>,Michigan Technological University, Department of Computer Science, June 1996.

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