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<!doctype html public "-//W30//DTD W3 HTML 2.0//EN"><HTML><TITLE>COMPUTER ARCHITECTURE GROUP</TITLE><center><!WA0><A HREF="http://www.cag.lcs.mit.edu/"><!WA1><IMG SRC=http://www.lcs.mit.edu/web_project/Brochure/cag/cagline.gif></a></center><p><center><table border><tr> <td><!WA2><img src=http://www.lcs.mit.edu/web_project/Brochure/cag/ward.gif></td> <td width=100 rowspan=2><br></td> <td><!WA3><img src=http://www.lcs.mit.edu/web_project/Brochure/cag/agarwal.gif></td></tr><tr><td> <address><b>Stephen A. Ward</b></a>,<br>Professor of Computer <br>Science and Engineering</address> </td><td><!WA4><A HREF="http://cag-www.lcs.mit.edu/~agarwal"><address><b>Anant Agarwal</b></a>,<br>Jamieson Career Development<br>Associate Professor of Computer Science</address></td></tr></table></center><body><p>Among the Computer Architecture group's research is aproject called NuMesh, which effectively combines"Tinkertoy" modularity with supercomputer performance.NuMesh describes a packaging and interconnect technologythat supports high-bandwidth systolic communications on anovel 3D four-neighbor nearest-neighbor lattice. NuMeshmodules simply plug together rather than being connected byprinted circuit traces or backplane buses.<p><!WA5><A HREF="http://cag-www.lcs.mit.edu:80/numesh/">NuMesh</a> explores an engineering discipline in which physicallocation of components are accounted for explicitly, ratherthan being abstracted out of the logical model. Simpleengineering models are provided via software tools insteadof hardware generality, much as RISC maintains itsprogramming model through compilation rather than throughprocessor complexity. Modularity of the communicationssubstrate provides regularity in the compilation target andallows iteration of a single communication building blockto replace a variety of ad hoc communication paths.<center><table border><tr> <td><!WA6><img src=http://www.lcs.mit.edu/web_project/Brochure/cag/pratt.gif></td> <td width=100 rowspan=2><br></td> <td><!WA7><img src=http://www.lcs.mit.edu/web_project/Brochure/cag/krantz.gif></td></tr><tr><td> <address><b>Gill Pratt</b><br> Assistant Professor of Computer <br>Science and Engineering</address> </td><td><!WA8><A HREF="http://cag-www.lcs.mit.edu/~krantz"><address><b>David A. Kranz,</b></a><br>Research Associate</address></td></tr></table></center><p>The cost/performance advantages of this approach stem fromthree factors. First, physical component placement isoptimized as part of the logical design. Secondly, theunderlying communication technology can be designed forperformance rather than interconnect flexibility. Andthirdly, interconnection relies on mass-produced modules,not on configuration-specific wiring.<p>NuMesh research embraces several technologies, includingarchitecture of the communications substrate; clocking andcommunication technologies; compilers and programmingmodels, and representative applications. Our initial focushas been the important class of algorithms whose staticcommunication patterns can be precompiled into a system ofindependent but carefully choreographed finite-statemachine descriptions. We also are exploring the extensionof NuMesh to more general communication -- to supportdynamic routing, for example.<p>On another front, the <!WA9><A HREF="http://cag-www.lcs.mit.edu:80/alewife/">Alewife</a> project was created to designa scalable, cache-coherent, shared-memory multiprocessor.In this program, several thousand VLSI processors, eachassociated with a portion of shared memory, areinterconnected via a multistage network. Unlikeconventional shared-memory machines, this multiprocessorexploits locality of referencing at the hardware andsoftware levels to maximize available memory bandwidth. Anew distributed directory ensures coherence of thehigh-speed caches each processor uses to store both privateand shared data, thus further utilizing locality.<p>Research focuses on data collection methods, analytical andsimulation techniques for evaluating large-scale parallelcomputers, and designing and building new interconnectionnetworks and processor-cache memory systems.<p>An important goal is to couple the design of algorithms forcompilers and operating systems to their goal-resultantimpact on multiprocessor performance. Address tracesobtained using various data collection techniques helpevaluate architectural choices. This insight in turn feedsback to software development.<p>A major part of the project investigates hardwaretechnologies and packaging for future high-density,low-latency interconnections.</BODY><p><!WA10><a href="http://www.lcs.mit.edu/web_project/Brochure/contents.html"><!WA11><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/contents_motif.gif></a><!WA12><a href="http://www.lcs.mit.edu/web_project/Brochure/cva/cva.html"><!WA13><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/previous_group_motif.gif></a><!WA14><a href="http://www.lcs.mit.edu/web_project/Brochure/csg/csg.html"><!WA15><img align=left src=http://www.lcs.mit.edu/web_project/Brochure/icons/next_group_motif.gif></a></HTML>⌨️ 快捷键说明
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