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Date: Mon, 11 Nov 1996 22:25:23 GMTServer: NCSA/1.4.2Content-type: text/html<html><head><title>Simultaneous Multithreading home page</title></head><body bgcolor="#ffffff" TEXT="#000000" ALINK="#0080C0"><h2><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><IMG align=centersrc="http://www.cs.washington.edu/research/smt/gif/smtlogo.gif"><a name=top>Simultaneous Multithreading Project</a></h2></center><p><hr><ul><li><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><a href="http://www.cs.washington.edu/research/smt/index.html#Overview">Overview</a><li><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.washington.edu/research/smt/index.html#People">People</a><li><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.cs.washington.edu/research/smt/index.html#Publications">Publications</a></ul><p><hr><p><a name="Overview"><h2> Overview</h2>The crucial problem facing today's high-speed microprocessors is maintaining high processor utilization in the face of long instruction and memory latencies. To alleviate this problem, modern processors issue multiple instructions per cycle (i.e., superscalars), or interleave the execution of differentthreads in different cycles (multithreaded processors). Ultimately, though, both techniques are limited by the amount of parallelism available within a single thread in a single cycle.<br><p> Simultaneous multithreading (SMT) is a technique that permits multiple independent threads to issue instructions to a superscalar's functional units in a single cycle. SMT combines the multiple-instruction-issuefeatures of wide superscalar processors with the latency-hiding abilityof multithreaded architectures. On an SMT processor, all hardware contextsare active simultaneously, competing each cycle for all available resources.This dynamic sharing of processor resources enables SMT to exploitthread-level and instruction-level parallelism interchangeably; both formsof parallelism can be effectively used to increase processor utilization.<p>Our studies havedemonstrated that simultaneous multithreading significantly improvesprocessor throughput and performance on both multiprogrammed and parallelworkloads. We have shown that these performance gains can be achievedin an architecture with only minimal extensions to modern out-of-ordersuperscalar processors.<br><p>Our current and future work includes investigations of fast synchronizationtechniques enabled by SMT. We are also conducting research in otherarchitectural and compiler issues for simultaneous multithreading.<p><hr><a name="People"><h2> People</h2><ul><h3>Faculty</h3><li> <!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="http://www.cs.washington.edu/homes/eggers">Susan Eggers</a><li> <!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href="http://www.cs.washington.edu/homes/levy">Hank Levy</a><h3>Graduate students</h3><li> <!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href="http://www.cs.washington.edu/homes/jlo">Jack Lo</a><li> <!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href="http://www.cs.washington.edu/homes/tullsen">Dean Tullsen</a><h3>Industrial collaborators (Digital Equipment Corporation)</h3><li> Joel S. Emer<li> Rebecca L. Stamm</ul><p><hr><p><a name="Publications"><h2> Publications</h2><ul><li><i> Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading</i> (<!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href="http://www.cs.washington.edu/research/smt/papers/tlpabstract.html">Abstract</a>, <!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><a href="http://www.cs.washington.edu/research/smt/papers/tlp2ilp.ps">Postscript</a>) <br><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><!WA10><a href="http://www.cs.washington.edu/homes/jlo">J.L. Lo</a>,<!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><!WA11><a href="http://www.cs.washington.edu/homes/eggers">S.J. Eggers</a>, J.S. Emer, <!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><!WA12><a href="http://www.cs.washington.edu/homes/levy">H.M. Levy</a>,R.L. Stamm, and<!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><!WA13><a href="http://www.cs.washington.edu/homes/tullsen">D.M. Tullsen</a> <br>Submitted for publication, July 1996.<br><br><li><i> Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor </i>(<!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><!WA14><a href="http://www.cs.washington.edu/research/smt/papers/isca96abstract.html">Abstract</a>, <!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><!WA15><a href="http://www.cs.washington.edu/research/smt/papers/ISCA96.ps">Postscript</a>) <br><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><!WA16><a href="http://www.cs.washington.edu/homes/tullsen">D.M. Tullsen</a>,<!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><!WA17><a href="http://www.cs.washington.edu/homes/eggers">S.J. Eggers</a>, J.S. Emer, <!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><!WA18><a href="http://www.cs.washington.edu/homes/levy">H.M. Levy</a>,<!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><!WA19><a href="http://www.cs.washington.edu/homes/jlo">J.L. Lo</a>,and R.L. Stamm <br>Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, May 1996.<br><br><li><i> Compilation Issues for a Simultaneous Multithreading Processor </i>(<!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><!WA20><a href="http://www.cs.washington.edu/research/smt/papers/smtc_abstract.ps">Postscript</a>) <br><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><!WA21><a href="http://www.cs.washington.edu/homes/jlo">J.L. Lo</a>, <!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><!WA22><a href="http://www.cs.washington.edu/homes/eggers">S.J. Eggers</a>, <!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><!WA23><a href="http://www.cs.washington.edu/homes/levy">H.M. Levy</a>, and<!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><!WA24><a href="http://www.cs.washington.edu/homes/tullsen">D.M. Tullsen</a> <br>Proceedings of the First SUIF Compiler Workshop, Stanford, CA, January 1996, p. 146-7.<br><br><li> <i>Simultaneous Multithreading: Maximizing On-Chip Parallelism</i> (<!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><!WA25><a href="http://www.cs.washington.edu/research/smt/papers/isca95abstract.html">Abstract</a>, <!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><!WA26><a href="http://www.cs.washington.edu/research/smt/papers/ISCA95.ps">Postscript</a>) <br><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><!WA27><a href="http://www.cs.washington.edu/homes/tullsen">D.M. Tullsen</a>,<!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><!WA28><a href="http://www.cs.washington.edu/homes/eggers">S.J. Eggers</a>, and<!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><!WA29><a href="http://www.cs.washington.edu/homes/levy">H.M. Levy</a>, <br>Proceedings of the 22rd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June 1995.<br><br></ul><p><hr><p><h2> UW students:</h2>Check the list of research projects still to doon the student-affairs page.<p></ul><hr>This page maintained by Jack Lo<br><address><em>jlo@cs.washington.edu </em> <br></address></body></html>⌨️ 快捷键说明
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